A number of unit cells of a digital-to-analog converter (DAC) may be simultaneously activated to generate an analog signal according to a decoded digital signal. However, while many unit cells may be generally the same, there may be variations in the gains associated with each unit cell (e.g., based on the locations of the activated unit cells within a unit cell array) amounting to a gain gradient that may cause error in the analog output. As such, a fill order may be set or selected to counter such variation by activating a particular arrangement of unit cells, as opposed to simply the number of unit cells, for a given digital signal. By filling the unit cell array from different sides, spatially and/or temporally, the gain gradient associated with the unit cells may be balanced to reduce error and increase the linearity of the DAC.

Described are apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, apparatus comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.

A digital-to-analog converter (DAC) and memory device includes an array of memory cells including resistive memory elements programmable between a high resistive and low resistive state. In implementations the array of memory cells is segmented into unary and binary coded sub-arrays. The device includes a binarizer configured to couple to the memory array to assign binary weights, or segmented unary and binary weights, to currents through a plurality of memory cells or voltages across a plurality of memory cells. The memory device further includes a summer to sum the weighted outputs of the binarizer. A current to voltage converter coupled with the summer generates an analog output voltage corresponding with digital data stored in a plurality of memory cells.

Methods, apparatus and articles of manufacture (e.g., physical storage media) to calibrate interpolating string digital-to-analog converters are disclosed. Example methods disclosed herein to calibrate a digital-to-analog converter (DAC) include determining a first calibration codeword based on a first nonlinearity error value measured at an output of the DAC when a most-significant-bit (MSB) portion of an input codeword is applied to an input of the DAC. Such disclosed example methods also include determining a second calibration codeword based on a second measured nonlinearity error value measured at the output of the DAC when a least-significant-bit (LSB) portion of the input codeword is applied to the input of the DAC. Such disclosed example methods further include combining the first calibration codeword and the second calibration codeword to determine a third calibration codeword to be accessed by the DAC to calibrate the output of the DAC when the input codeword is applied to the DAC.

Apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. are provided here. An apparatus is provided which comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.

Methods, apparatus and articles of manufacture (e.g., physical storage media) to calibrate interpolating string digital-to-analog converters are disclosed. Example methods disclosed herein to calibrate a digital-to-analog converter (DAC) include determining a first calibration codeword based on a first nonlinearity error value measured at an output of the DAC when a most-significant-bit (MSB) portion of an input codeword is applied to an input of the DAC. Such disclosed example methods also include determining a second calibration codeword based on a second measured nonlinearity error value measured at the output of the DAC when a least-significant-bit (LSB) portion of the input codeword is applied to the input of the DAC. Such disclosed example methods further include combining the first calibration codeword and the second calibration codeword to determine a third calibration codeword to be accessed by the DAC to calibrate the output of the DAC when the input codeword is applied to the DAC.

Described is an apparatus having a non-linear control to manage power supply droop at an output of a voltage regulator. The apparatus comprises: a first inductor for coupling to a load; a capacitor, coupled to the first inductor, and for coupling to the load; a first high-side switch couple to the first inductor; a first low-side switch coupled to the first inductor; a bridge controller to control when to turn on and off the first high-side and first low-side switches; and a non-linear control (NLC) unit to monitor output voltage on the load, and to cause the bridge controller to turn on the first high-side switch and turn off the first low-side switch when a voltage droop is detected on the load.

A successive approximation ADC made of a low voltage configurable differential amplifier and low voltage logic circuits which can convert a high voltage analog input to a digital equivalent. The differential amplifier can be configured as either an op amp or a comparator depending upon the mode of operation. An input capacitor C1 is switchably coupled to an electrode selected for voltage sampling. A switched capacitor array C2 is coupled across the differential amplifier input and output. A SAR coupled to the switched capacitor array provides a digital output corresponding to the sampled analog voltage. During a sampling interval and a charge transfer interval, the differential amplifier is configured as an op amp. During the transfer interval, the voltage on the input capacitor multiplied by the ratio C1/C2 is transferred to the switched capacitor array. During an analog to digital conversion interval, the ADC converts the analog voltage to an equivalent digital output.

Methods, apparatus and articles of manufacture (e.g., physical storage media) to calibrate interpolating string digital-to-analog converters are disclosed. Example methods disclosed herein to calibrate a digital-to-analog converter (DAC) include determining a first calibration codeword based on a first nonlinearity error value measured at an output of the DAC when a most-significant-bit (MSB) portion of an input codeword is applied to an input of the DAC. Such disclosed example methods also include determining a second calibration codeword based on a second measured nonlinearity error value measured at the output of the DAC when a least-significant-bit (LSB) portion of the input codeword is applied to the input of the DAC. Such disclosed example methods further include combining the first calibration codeword and the second calibration codeword to determine a third calibration codeword to be accessed by the DAC to calibrate the output of the DAC when the input codeword is applied to the DAC.

Described are apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, apparatus comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.