An input sensing unit includes a touch sensing unit, which includes a plurality of driving electrodes, a plurality of sensing electrodes, and a driving signal generating unit which provides driving signals to the driving electrodes. The sensing electrodes are insulated from and intersect the driving electrodes. The driving signal generating, unit includes touch drivers connected to driving electrodes and a digital-to-analog converter configured to provide a first signal or a second signal, and each of the touch drivers is connected to a preset number of driving electrodes among the driving electrodes.

The disclosure discloses a temperature compensation circuit and method for a neural network computing-in-memory array. Reference arrays sparsely inserted in the computing-in-memory array are adopted to provide a reference voltage for ADCs, so that an input voltage and a reference voltage of the ADCs have a same temperature coefficient. Finally, after analog-to-digital conversion by the ADC, the digital output of the ADC is not affected by the external temperature, thereby ensuring the operational precision of the neural network. According to the temperature compensation circuit of the disclosure, the reference arrays have the same structure as the computing-in-memory array. The insertion density of the reference arrays is related to the temperature field where the computing-in-memory arrays are located. One reference array may provide the reference voltage of the ADC for a plurality of computing-in-memory arrays, thereby minimizing the increase of area and power consumption caused by inserting the reference arrays.

Systems, apparatuses, and methods for performing digital pre-distortion compensation of digital-to-analog converter non-linearity are described. A correction circuit receives a digital input word and couples a portion of the most significant bits (MSB's) of the digital input word to a correction lookup table (LUT). A correction value is retrieved from a correction LUT entry that matches the MSB's of the digital input word. Next, the correction value is added to the original digital input word in the digital domain. Then, the sum generated by adding the correction value to the original digital input word is optionally clipped if the sum exceeds the DAC core's input range. Next, the DAC core converts the sum into an analog value that is representative of the digital input word. The above approach helps to reduce non-linearities introduced by the DAC core in an energy-efficient manner by performing a correction in the digital domain.

An apparatus for canceling an input offset of a receiver including a differential amplification unit and a differential comparison unit in a distance sensing system includes: an output monitoring unit selectively monitoring differential outputs of the differential comparison unit and the differential amplification unit; a current type digital-analog conversion unit connected to each of an input terminal of the differential comparison unit and the input terminal of the differential amplification unit; and a control unit controlling the current type digital-analog conversion unit to reduce a difference in differential output of the differential comparison unit according to a comparison result for the difference of the monitored differential output of the differential comparison unit and controlling the current type digital-analog conversion unit to reduce the difference in differential output of the differential amplification unit according to the comparison result for the difference of the monitored differential output of the differential amplification unit.

An apparatus for canceling an input offset of a receiver including a differential amplification unit and a differential comparison unit in a distance sensing system includes: an output monitoring unit selectively monitoring differential outputs of the differential comparison unit and the differential amplification unit; a current type digital-analog conversion unit connected to each of an input terminal of the differential comparison unit and the input terminal of the differential amplification unit; and a control unit controlling the current type digital-analog conversion unit to reduce a difference in differential output of the differential comparison unit according to a comparison result for the difference of the monitored differential output of the differential comparison unit and controlling the current type digital-analog conversion unit to reduce the difference in differential output of the differential amplification unit according to the comparison result for the difference of the monitored differential output of the differential amplification unit.

Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.

Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.

Systems, methods, and devices are described for generating multi-tone waveforms. A count signal having a count value is generated. A plurality of step values and a plurality of phase values are received. For each increment of the count value, an index value corresponding to each step value of the plurality of step values is calculated based on the step value, the count value, and a respective phase value of the plurality of phase values. A tone point value corresponding to each calculated index value is determined to generate a plurality of tone point values for each increment of the count value. The determined tone point values are summed to generate a corresponding waveform point for each increment of the count value. A waveform is generated as a sequence of generated waveform points.

Examples herein relate to circuits for computing vector-matrix multiplications involving negative values. A first memory crossbar array may be mapped to a first matrix which includes the positive values of an input matrix. A second memory crossbar array may be mapped to a second matrix which includes the negative values of the input matrix. An analog-to-digital converter may generate digital intermediate multiplication results based on analog results computed by the memory crossbar arrays. The digital intermediate multiplication results may include an intermediate result corresponding to a multiplication of each of the first vector and second vector with each of the first matrix and the second matrix. A controller may aggregate the digital intermediate results to generate a combined multiple result that represents the vector-matrix multiplication of the input vector and the input matrix.

Examples herein relate to circuits for computing vector-matrix multiplications involving negative values. A first memory crossbar array may be mapped to a first matrix which includes the positive values of an input matrix. A second memory crossbar array may be mapped to a second matrix which includes the negative values of the input matrix. An analog-to-digital converter may generate digital intermediate multiplication results based on analog results computed by the memory crossbar arrays. The digital intermediate multiplication results may include an intermediate result corresponding to a multiplication of each of the first vector and second vector with each of the first matrix and the second matrix. A controller may aggregate the digital intermediate results to generate a combined multiple result that represents the vector-matrix multiplication of the input vector and the input matrix.