The disclosure belongs to the field of integrated circuits, and is used for reducing an area overhead and a power consumption of a pipelined analog-to-digital converter. Each stage of the pipelined analog-to-digital converter according to the disclosure comprises an analogue-to-digital converter, a digital-to-analog converter, a subtractor and an amplifier. According to the disclosure, an amplification time of the pipelined ADC is used for extra quantization, and a number of bits of each ADC is reduced on the premise of not increasing a number of stages of the pipelined ADC, so that a scale of each circuit is greatly reduced, and the power consumption and the area overhead are reduced.

A Digital-to-Analog Converter (DAC) is provided. The DAC includes a code converter circuit configured to sequentially receive first digital control codes for controlling N digital-to-analog converter cells. N is an integer greater than one. The code converter circuit is further configured to convert the first digital control codes to second digital control codes. Additionally, the DAC includes a bit-shifter circuit configured to receive shift codes for the second digital control codes. The shift codes are obtained using dynamic element matching and indicate a respective circular shift by r.sub.i bit positions for the i-th second digital control code, wherein r.sub.i is an integer smaller than N−1. The bit-shifter circuit is further configured to generate third digital control codes by circularly shifting the second digital codes based on the shift codes. In addition, the DAC includes a cell activation circuit configured to selectively activate one or more of the N digital-to-analog converter cells based on the third digital control codes.

A Digital-to-Analog Converter (DAC) is provided. The DAC includes a code converter circuit configured to sequentially receive first digital control codes for controlling N digital-to-analog converter cells. N is an integer greater than one. The code converter circuit is further configured to convert the first digital control codes to second digital control codes. Additionally, the DAC includes a bit-shifter circuit configured to receive shift codes for the second digital control codes. The shift codes are obtained using dynamic element matching and indicate a respective circular shift by r.sub.i bit positions for the i-th second digital control code, wherein r.sub.i is an integer smaller than N−1. The bit-shifter circuit is further configured to generate third digital control codes by circularly shifting the second digital codes based on the shift codes. In addition, the DAC includes a cell activation circuit configured to selectively activate one or more of the N digital-to-analog converter cells based on the third digital control codes.

This disclosure describes systems, methods, and apparatus for a digital-to-analog (DAC) converter, that can be part of a variable capacitor and/or a match network. The DAC can include a digital input, an analog output, N contributors (e.g., switched capacitors), and an interconnect topology connecting the N contributors, generating a sum of their contributions (e.g., sum of capacitances), and providing the sum to the analog output. The N contributors can form a sub-binary sequence when their contributions to the sum are ordered by average contribution. Also, the gap size between a maximum contribution of one contributor, and a minimum contribution of a subsequent contributor, is less than D, where D is less than or equal to two time a maximum contribution of the first or smallest of the N contributors.

This disclosure describes systems, methods, and apparatus for a digital-to-analog (DAC) converter, that can be part of a variable capacitor and/or a match network. The DAC can include a digital input, an analog output, N contributors (e.g., switched capacitors), and an interconnect topology connecting the N contributors, generating a sum of their contributions (e.g., sum of capacitances), and providing the sum to the analog output. The N contributors can form a sub-binary sequence when their contributions to the sum are ordered by average contribution. Also, the gap size between a maximum contribution of one contributor, and a minimum contribution of a subsequent contributor, is less than D, where D is less than or equal to two time a maximum contribution of the first or smallest of the N contributors.

An interventional control method based on a computer control system. An interventional control system is designed on the basis of an original computer control system; the analog-to-digital conversion unit of the interventional control system receives a signal from the data acquisition module of the original computer control system and said signal is processed by a control processing unit according to a built-in program; then a digital-to-analog conversion unit performs digital-to-analog conversion on the signal output by the control processing unit and then outputs a signal obtained after the digital-to-analog conversion to the analog-to-digital conversion unit of the original computer control system. According to the interventional computer control system, on the basis of an original computer control system, the analog-to-digital conversion unit of the interventional control system receives a signal output from the data acquisition module of the original computer control system and control processing is performed on said output signal; then the digital-to-analog conversion unit of the interventional control system outputs a signal to the analog-to-digital conversion unit of the original computer control system. The function upgrade of an original computer control system is implemented without changing the operating program of the original computer control system.

An interventional control method based on a computer control system. An interventional control system is designed on the basis of an original computer control system; the analog-to-digital conversion unit of the interventional control system receives a signal from the data acquisition module of the original computer control system and said signal is processed by a control processing unit according to a built-in program; then a digital-to-analog conversion unit performs digital-to-analog conversion on the signal output by the control processing unit and then outputs a signal obtained after the digital-to-analog conversion to the analog-to-digital conversion unit of the original computer control system. According to the interventional computer control system, on the basis of an original computer control system, the analog-to-digital conversion unit of the interventional control system receives a signal output from the data acquisition module of the original computer control system and control processing is performed on said output signal; then the digital-to-analog conversion unit of the interventional control system outputs a signal to the analog-to-digital conversion unit of the original computer control system. The function upgrade of an original computer control system is implemented without changing the operating program of the original computer control system.

A semiconductor device with low power consumption is provided. The semiconductor device includes a first layer and a second layer. The first layer includes a first cell and a first to a third circuit, and the second layer includes a second cell and a fourth and a fifth circuit. The first, second, and fourth circuits each have a function of converting digital data into analog current. The first cell calculates a product of a value from the first current and a value from the second circuit and inputs a calculation result into a third circuit as current. The third circuit generates analog current from the input current. The second cell calculates a product of a value from the third circuit and a value from the fourth circuit and inputs a calculation result into the fifth circuit as current. The fifth circuit generates analog current from the input current.

A semiconductor device with low power consumption is provided. The semiconductor device includes a first layer and a second layer. The first layer includes a first cell and a first to a third circuit, and the second layer includes a second cell and a fourth and a fifth circuit. The first, second, and fourth circuits each have a function of converting digital data into analog current. The first cell calculates a product of a value from the first current and a value from the second circuit and inputs a calculation result into a third circuit as current. The third circuit generates analog current from the input current. The second cell calculates a product of a value from the third circuit and a value from the fourth circuit and inputs a calculation result into the fifth circuit as current. The fifth circuit generates analog current from the input current.

An optical sensor arrangement comprises a photodiode and a converter arrangement including an integration amplifier, a comparator amplifier, an integration capacitor and a result register. During a precharge phase the result register is set to a starting value. During an integration phase a current is sampled through the photodiode to update the result register in response to down charges applied to an input of the integration amplifier. During a residue phase the result register is updated in dependence on the charge remaining on the integration capacitor. Measuring the residual charge increases resolution and accuracy of the converter.