In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Hardware circuitry defines logic for both Sbox generation and inverse Sbox generation via generating a multiplicative inverse matrix as a truth table for data. The hardware circuitry receives input plain text to be encrypted. The hardware circuitry divides the input plain text to be encrypted. The hardware circuitry feeds multiplicative inverse values generated from the input plain text to a transformer module for performing affine to encrypt the plain text data. The hardware circuitry receives encrypted data to be decrypted. The hardware circuitry divides the encrypted data to be decrypted. The hardware circuitry feeds multiplicative inverse generated from the encrypted data to the transformer module for performing inverse affine to decrypt the encrypted data.

A data processing method, an apparatus, and a device are disclosed. The data processing method may be performed by a first communications device, and the first communications device is a transmit end of encoded data. The first communications device may send a high-order signal to a second communications device by using a plurality of parallel channels, and information bits in the parallel channels are arranged in a specified order. The method helps improve a transmission rate in a parallel channel transmission scenario, and helps the second communications device perform correct decoding.

A data processing method and apparatus. The data process method includes: determining, by a transmitting node, a code block length N.sub.0 for encoding an information bit sequence to be transmitted according to a data characteristic for representing the information bit sequence to be transmitted and a preset parameter corresponding to the data characteristic; performing, by the transmitting node, polar encoding on the information bit sequence to be transmitted according to the code block length N.sub.0; and transmitting, by the transmitting node, a code block obtained through the polar encoding to a receiving node.

A cyclic redundancy check, CRC, computation circuit comprising an input for receiving an input stream having an input bit sequence comprising two or more bits at a time aligned to rows of a CRC generator matrix stored in a Look Up Table, LUT; a set of two or more parallel processors configured to perform a CRC computation of the input bit sequence; wherein the LUT comprises a plurality of addresses wherein at least one of the addresses is configured to store two or more rows of the CRC generator matrix; and the set of parallel processors is configured to: combine LUT data with the input stream by using two or more bits of the aligned input stream to mask the two or more rows of the CRC generator matrix stored in the LUT; and combine generated two or more intermediate parity bit sequences into a single parity bit sequence.

A cyclic redundancy check, CRC, decoder circuit having a K-bit input bit sequence, s, comprising information bits and CRC bits; and at least one processor (P) configured to perform a CRC decode computation and configured to: use an inverse of a predefined CRC generator polynomial that encoded the K-bit input bit sequence, s, to produce a data set; compute a CRC syndrome from the data set; and determine whether the CRC syndrome contains any one-valued bits indicative of a CRC error. An LUT stores one or more rows of a CRC generator matrix (G) generated from the inverse of the predefined CRC generator polynomial. A set of mod(−K,P) zero-valued filler bits are appended to an end of the K-bit input bit sequence, wherein an order of the rows in the CRC generator matrix (G) is reversed and aligned with the input bits of the input stream.

A circuit for generating an N-bit cyclic redundancy code of a k-bit digit d, the code based on a reconfigurable generator polynomial P of degree N, the circuit including a dynamic table comprising a multiplication sub-table storing products resulting from multiplication by the polynomial P of each element definable over k bits, in the order of the scalar values of the k-bit elements; a division sub-table storing quotients resulting from Euclidean division by the polynomial P of each k-bit element shifted by N bits to the left, in the order of the scalar values of the k-bit elements; and a group of first multiplexers, each multiplexer connected to be indexed by a respective cell of the division table to transmit the contents of a corresponding cell of the multiplication table to an output of the dynamic table, of same rank as the respective cell of the division table.

A memory system includes a non-volatile memory and a controller. The controller is configured to, during a writing operation, generate a first error-detecting code from data that is input, perform a predetermined conversion on the data into first conversion data, generate a second error-detecting code from the first conversion data, and store the data, the first error-detecting code, and the second-error detecting code in the non-volatile memory. The controller is configured to during a read operation, read the data, the first error-detecting code, and the second error-detecting code from the non-volatile memory, perform a first error detection on the data using the first error-detecting code, perform the predetermined conversion on the data into second conversion data, perform a second error detection on the second conversion data using the second error-detecting code, and output the second conversion data based on results of the first and second error detections.

In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

A circuit with an interface, a transmit data register coupled to the interface, a storage device coupled to the transmit data register and including a plurality of storage locations, each storage location adapted to store a data unit, and a serial register coupled between the storage device and an output. The circuit also includes a CRC generation circuit having an input coupled between an output of the transmit data register and the storage device. The CRC generation circuit includes a first CRC generation block for providing a CRC in response to an X-bit data unit and an X-bit polynomial and a second CRC generation block with a collective X-bit input for providing a CRC in response to an X-bit data unit and a 2X-bit polynomial in a single clock cycle and a 2X-bit data unit and a 2X-bit polynomial in two clock cycles.