Apparatuses, systems, and methods for multi-bit error detection. A memory device may store data bits and parity bits in a memory array. An error correction code (ECC) circuit may generate syndrome bits based on the data and parity bits and use the syndrome bits to correct up to a single bit error in the data and parity bits. A multi-bit error (MBE) detection circuit may detect an MBE in the data and parity based on at least one of the syndrome bits or the parity bits. For example, the MBE detection circuit may determine if the syndrome bits have a mapped or unmapped state and/or may compare the parity bits, data bits, and an additional parity bit to determine if there is an MBE. When an MBE is detected an MBE signal is activated. In some embodiments, an MBE flag may be set based on the MBE signal being active.

A storage device includes: a memory; and a processor configured to, at the time of writing data into the memory, generate a first check code common to a plurality of types of error correction codes from the data on the basis of a correlation relationship between the plurality of types of error correction codes, add the first check code to the data and write the data into the memory, convert the first check code into a second check code based on any one of the plurality of types of error correction codes at the time of reading the data from the memory, and perform error correction by using the second check code.

A storage device includes: a memory; and a processor configured to, at the time of writing data into the memory, generate a first check code common to a plurality of types of error correction codes from the data on the basis of a correlation relationship between the plurality of types of error correction codes, add the first check code to the data and write the data into the memory, convert the first check code into a second check code based on any one of the plurality of types of error correction codes at the time of reading the data from the memory, and perform error correction by using the second check code.

Apparatuses, systems, and methods for multi-bit error detection. A memory device may store data bits and parity bits in a memory array. An error correction code (ECC) circuit may generate syndrome bits based on the data and parity bits and use the syndrome bits to correct up to a single bit error in the data and parity bits. A multi-bit error (MBE) detection circuit may detect an MBE in the data and parity based on at least one of the syndrome bits or the parity bits. For example, the MBE detection circuit may determine if the syndrome bits have a mapped or unmapped state and/or may compare the parity bits, data bits, and an additional parity bit to determine if there is an MBE. When an MBE is detected an MBE signal is activated. In some embodiments, an MBE flag may be set based on the MBE signal being active.

Automatic Repeat Request (ARQ) protocol is used in many modern telecommunication systems for improved link level reliability. Hybrid ARQ (HARQ) protocol takes advantage of the retransmissions in ARQ to enable the receiver to decode the currently received data by combining it with all the previously received transmissions that were not successfully decoded. Each successive retransmission improves the probability of correctly decoding the data. To support HARQ, the receiver is required to store the previously received unsuccessful transmissions for combining with future retransmissions. The storage of the previously received unsuccessful transmissions can be very large depending on type of the HARQ protocol used. A method and apparatus are disclosed that enable reduced memory storage requirements while maintaining the HARQ performance requirements. The reduced memory requirements result in reduced cost, reduced power consumption and lowered cost.

A memory system includes; a memory device, a memory controller including a first interface, a second interface, and a first data processor having a first error correction code (ECC) engine, and a field programmable gate array (FPGA) including a third interface connected to the first interface, a fourth interface connected to the second interface, a fifth interface connected to an external host, and a second data processor having a second ECC engine. The memory controller may configure a normal write operation path or highly reliable write operation path.

A memory system includes; a memory device, a memory controller including a first interface, a second interface, and a first data processor having a first error correction code (ECC) engine, and a field programmable gate array (FPGA) including a third interface connected to the first interface, a fourth interface connected to the second interface, a fifth interface connected to an external host, and a second data processor having a second ECC engine. The memory controller may configure a normal write operation path or highly reliable write operation path.

Various aspects of the disclosure relate to encoding information and decoding information. In some aspects, the disclosure relates to an encoder and a decoder for Polar codes with HARQ. If a first transmission of the encoder fails, information bits associated with a lower quality channel may be retransmitted. At the decoder, the resulting decoded retransmitted bits may be used to decode the first transmission by substituting the retransmitted bits for the original corresponding (low quality channel) bits. In some aspects, to decode the first transmission, soft-combining is applied to the decoded retransmitted bits and the original corresponding (low quality channel) bits. In some aspects, CRC bits for a first transmission may be split between a first subset of bits and a second subset of bits. In this case, the second subset of bits and the associated CRC bits may be used for a second transmission (e.g., a retransmission).

A device for monitoring a digital control unit with regard to functional safety is proposed. The device comprises an interface configured to receive a control signal of the digital control unit for a circuit component. The control signal represents a digital value. Furthermore, the device comprises a timer circuit configured to output an associated timer value in each case for successive points in time. The device furthermore comprises a hash value generator, which is configurable, in response to a change in the digital value, to recalculate a hash value on the basis of the change in the digital value and the timer value at the point in time of the change in the digital value.

The present technology includes a controller and a memory system including the same. The controller includes a memory interface configured to receive a codeword from a memory device, and an error correction circuit configured to: perform an error correction decoding operation on the codeword received from the memory interface, compare a number of unsatisfied check nodes (UCNs) detected in the error correction decoding operation with a reference number, perform or stop the error correction decoding operation on the codeword according to a result of comparing the number of UCNs and the reference number, and output a retransmission request signal of the codeword to the memory interface in response to the result, wherein the memory interface requests the codeword to the memory device in response to the retransmission request signal.