An operating method of a memory device includes storing position information regarding a codeword including an erasure and erasure information including position information regarding the erasure in a memory region, loading the position information regarding the codeword to a row decoder and a column decoder, determining whether a read address corresponding to a read instruction is identical to the position information regarding the codeword including the erasure, in response to the read instruction from a host, transmitting the position information of the erasure to an error correction code (ECC) decoder, when the read address is identical to the position information regarding the codeword including the erasure, and correcting, by the ECC decoder, an error in a codeword received from a memory cell array using the position information regarding the erasure.

Methods, systems, and apparatuses include receiving a codeword stored in a memory device. Energy function values are determined for bits of the codeword based on soft information for the bits of the codeword. A bit of the codeword is flipped when the energy function values for a bit of the codeword satisfies a bit flipping criterion. A corrected codeword that results from the flipping of the bits is returned.

A decoding device includes a controller classifying a bitstream as a first bitstream and a second bitstream based on a plurality of blocks defined by a matrix and included in a frame, a first decoder including a first processor performing decoding on the first bitstream and outputting first decoding data and a first memory, a second decoder including a second processor performing decoding on the second bitstream and outputting second decoding data and a second memory, a first buffer transmitting the first decoding data to the second memory, and a second buffer transmitting the second decoding data to the first memory. The first processor controls the second memory to store the first decoding data, and the second processor controls the first memory to store the second decoding data.

An optimal detection voltage obtaining method, a reading control method and an apparatus are provided. The method includes: obtain a plurality of first difference values and a plurality of second difference values, the second difference value characterizes a difference value of two detection voltages which are adjacent in numerical value, the first difference value characterizes a difference between numbers of memory cells whose threshold voltages respectively equal to the two detection voltages used by the second difference value; dividing the first difference by the second difference to obtain a plurality of tangent approximations; selecting a first tangent approximation and a second tangent approximation from the plurality of tangent approximations, the first tangent approximation is a positive number and the second tangent approximation is a negative number; calculating an optimal detection voltage according to the first tangent approximation, the second tangent approximation, a first detection voltage and a second detection voltage.

A decoding method for low density parity code is provided. The method includes performing an iterative decoding operation for a codeword, wherein a plurality of Log-Likelihood-Ratios correspond respectively to a plurality of data bits of the codeword; determining whether the iterative decoding operation is successful; determining whether a perturbation condition is met if the iterative decoding operation is not successful; performing protect operation for a first Log-Likelihood-Ratio among the Log-Likelihood-Ratios, and performing a perturbation operation for a plurality of second Log-Likelihood-Ratios among the Log-Likelihood-Ratios, wherein the second Log-Likelihood-Ratios are different to the first Log-Likelihood-Ratio; and re-performing the iterative decoding operation for the codeword after finishing the perturbation operation.

A decoding method, a memory storage device, and a memory control circuit unit are provided. The decoding method includes: reading a codeword from a memory module and estimating error level information of the codeword; inputting the codeword and the error level information to an error checking and correcting circuit through a first message channel and a second message channel respectively; determining whether the error level information meets a default condition; if yes, inputting the codeword to a first decoding engine of the error checking and correcting circuit for decoding; otherwise, inputting the codeword to a second decoding engine of the error checking and correcting circuit for decoding, wherein a power consumption of the first decoding engine is lower than that of the second decoding engine, and a decoding success rate of the first decoding engine is lower than that of the second decoding engine. Therefore, an operating flexibility for decoding may be improved.

Adaptive read threshold voltage tracking techniques are provided that employ bit error rate estimation based on a non-linear syndrome weight mapping. An exemplary device comprises a controller configured to determine a bit error rate for at least one of a plurality of read threshold voltages in a memory using a non-linear mapping of a syndrome weight to the bit error rate for the at least one of the plurality of read threshold voltages.

A memory device having a Low-Density Parity-Check (LDPC) decoder that is energy efficient and has a low error floor. The decoder is configured to determine syndromes of bits in a codeword, select bits in the codeword based at least in part on the syndromes according to a first mode, and flip the selected bits in the codeword. The decoder can repeat the bit selection and flipping operations to iteratively improve the codeword and reduce parity violations. Further, the decoder can detect a pattern in parity violations of the codeword in its iterative bit flipping operations. In response, the decoder can change from the first mode to a second mode in bit selection for flipping. For example, the decoder can transmit from a dynamic syndrome mode to a static syndrome mode in response to the pattern of repeating a cycle of bit flipping iterations.

A low-density parity-check (LDPC) decoder comprising a pre-processor, a core decoder, and a post-processor. The pre-processor is configured to transform a received log-likelihood-ratio (LLR) sequence into a form that enables the core decoder to toggle at a reduced rate during iterative decoding processing thereof. Upon stoppage of the decoding processing corresponding to the LLR sequence, the post-processor operates to apply a complementary transformation to the output of the core decoder, which recovers the corresponding codeword of the LDPC code. An example embodiment of the LDPC decoder operating in this manner may be able to beneficially reduce the power consumption therein by about 10%.

A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.