Systems and methods which provide parallel processing of multiple message bundles for a codeword undergoing a decoding process are described. Embodiments provide low-latency segmented quasi-cyclic low-density parity-check (QC-LDPC) decoder configurations in which decoding process tasks are allocated to different segments of the low-latency segmented QC-LDPC decoder for processing multiple bundles of messages in parallel. A segmented shifter of a low-latency segmented QC-LDPC decoder implementation may be configured to process multiple bundles of a plurality of edge paths in parallel. Multiple bundles of messages of a same check node cluster (CNC) are processed in parallel. Additionally, multiple bundles of messages of a plurality of CNCs are processed in parallel.

Systems and methods which provide parallel processing of multiple message bundles for a codeword undergoing a decoding process are described. Embodiments provide low-latency segmented quasi-cyclic low-density parity-check (QC-LDDC) decoder configurations in which decoding process tasks are allocated to different segments of the low-latency segmented QC-LDPC decoder for processing multiple bundles of messages in parallel. A segmented shifter of a low-latency segmented QC-LDPC decoder implementation may be configured to process multiple bundles of a plurality of edge paths in parallel. Multiple bundles of messages of a same check node cluster (CNC) are processed in parallel. Additionally, multiple bundles of messages of a plurality of CNCs are processed in parallel.

A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.

A method reducing amount of memory utilized by hybrid automatic repeat request (HARQ) operations is disclosed. When an apparatus employing the method receives an LDPC encoded packet, the apparatus firstly estimates a signal quality value of the received packet, and performs an LDPC decoding algorithm on the received packet. If the received packet is not successfully decoded by the apparatus, the received and decoding-failed packet is compressed in order to reduce bit-width, and the compressed packet is stored in a memory device for later HARQ operations. The apparatus employing the method is also disclosed.

Example systems, read channel circuits, data storage devices, and methods to use inter-symbol interference message passing (ISI-MP) data in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector, configured to determine both the first most likely and second most likely sets of symbols and output inter-symbol interference data based on the adjacent symbols and corresponding ISI in each set of symbols. The inter-symbol interference data may be used by an ISI-MP circuit configured to model ISI-MP and provide feedback to an iterative decoder during local iterations.

The complexity of sparse code multiple access (SCMA) decoding can be reduced by pruning codebooks to remove unlikely codewords prior to, or while, performing an iterative message passing algorithm (MPA). The pruned codebook is then used by to perform one or more iterations of MPA processing, thereby reducing the number codeword probabilities that are calculated for the corresponding SCMA layer. The pruned codebook also reduces the computational complexity of calculating codeword probabilities associated with other SCMA layers. The pruned codebook may be “reset” by reinserting the pruned codewords into the codebook after a final hard-decision for a given set of received samples is made, so that the pruning does not affect evaluation of the next set of samples.

A method and apparatus for decoding quasi-cyclic LDPC codes using a vertical layered iterative message passing algorithm. The algorithm of the method improves the efficiency of the check node update by using one or more additional magnitudes, predicted with predictive magnitude maps, for the computation of messages and update of the check node states. The method allows reducing the computational complexity, as well as the storage requirements, of the processing units in the check node update. Several embodiments for the apparatus are presented, using one or more predictive magnitude maps, targeting significant savings in resource usage and power consumption, while minimizing the impact on the error correction performance loss.

Low-density parity-check (LDPC) coding based on memory cell voltage distribution (CVD) in data storage devices. In one embodiment, a memory controller includes a memory interface configured to interface with a non-volatile memory; and a controller. The controller is configured to receive a plurality of data pages to be stored in the non-volatile memory, and transform the plurality of data pages into a plurality of transformed data pages. The controller is further configured to determine a plurality of parity bits based on the plurality of transformed data pages, and store the plurality of data pages and the plurality of parity bits in the non-volatile memory.

A method reducing amount of memory utilized by hybrid automatic repeat request (HARQ) operations is disclosed. When an apparatus employing the method receives an LDPC encoded packet, the apparatus firstly estimates a signal quality value of the received packet, and performs an LDPC decoding algorithm on the received packet. If the received packet is not successfully decoded by the apparatus, the received and decoding-failed packet is compressed in order to reduce bit-width, and the compressed packet is stored in a memory device for later HARQ operations. The apparatus employing the method is also disclosed.

Methods and apparatus for decoding LDPC code provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. A configurable LDPC decoder supporting many different LDPC codes having any sub-matrix size includes several independently addressable memories which are used to store soft decision data for each bit node. The decoder further includes a number P of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is P.sub.CNB (where P≥P.sub.CNB) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than P.sub.CNB*q bits.