A system for a fiber-optic network includes a transceiver. The transceiver includes a fiber-optic interface unit and a host unit. The host unit includes a low-complexity error correction decoder and a high-complexity error correction decoder. One or both from the low-complexity error correction decoder and the high-complexity error correction decoder are selected to decode input data from the fiber-optic interface unit, the input data including codewords.

A decoding method adopting an algorithm with weight-based adjusted parameters and a decoding system are provided. The decoding method is applied to a decoder. M×N low density parity check codes (LDPC codes) having N variable nodes and M check nodes are generated from input signals. In the decoding method, information of the variable nodes and the check nodes is initialized. The information passed from the variable nodes to the check nodes is formed after multiple iterations. After excluding a connection to be calculated, a product of the remaining connections between the variable nodes and the check nodes is calculated. Next, an estimated first minimum or an estimated second minimum can be calculated with multi-dimensional parameters. The information passed from the check nodes to the variable nodes can be updated for making a decision.

A method for decoding a low-density parity-check (LDPC) code, performed by a communication apparatus, includes: updating a variable node; determining n minimum values based on a min-sum algorithm (MSA); determining n indices based on the n minimum values; updating a check node using the n indices; calculating a log-likelihood ratio (LLR) value when the update of the check node is completed; and determining an information bit based on the LLR value.

The disclosure relates to a method performed by an apparatus for decoding an encoded signal in a communication system according to an embodiment of the disclosure may include an operation of receiving an encoded signal including a plurality of codeword bits, an operation of determining a first log-likelihood ratio (LLR) for the plurality of codeword bits, and an operation of performing iterative decoding a predetermined number of times based the first LLR, and the plurality of codeword bits may include a codeword bit included in a first subset and a codeword bit included in a second subset, and the operation of performing iterative decoding may include determining a second LLR only for the codeword bit included in the first subset of the plurality of codeword bits, and estimating, based on the second LLR, a bit value only for the codeword bit included in the first subset.

Devices for using a neural network to choose an optimal error correction algorithm are disclosed. An example device includes a decoding controller inputting at least one of the number of primary unsatisfied check nodes (UCNs), the number of UCNs respectively corresponding to at least one iteration, and the number of correction bits respectively corresponding to the at least one iteration to a trained artificial neural network, and selecting any one of a first error correction decoding algorithm and a second error correction decoding algorithm based on an output of the trained artificial neural network corresponding to the input, and an error correction decoder performing error correction decoding on a read vector using the selected error correction decoding algorithm. The output of the trained artificial neural network may include a first predicted value indicating a possibility that a first error correction decoding using the first error correction decoding algorithm is successful.

An ECC decoder includes: a memory comprising a memory region; a first converter configured to transmit a hard bit, received from a channel, to the memory to store the hard bit in a first area of the memory region; a second converter configured to receive the hard bit read from the first area and output a reliability value corresponding to the hard bit, whenever a hard decoding operation on the hard bit is iterated; and a variable node configured to perform the hard decoding operation using the reliability value.

The present disclosure relates to a method, system, and non-transitory computer-readable storage medium for constructing a base matrix of a PBRL LDPC code, comprising: determining at least one candidate sub-matrix of a PBRL LDPC code based on a base matrix of a QR-QC-LDPC code; obtaining at least one count of cycles with at least one preset length for each of the at least one candidate sub-matrix; and determining a first sub-matrix of the base matrix of the PBRL LDPC code based on the at least one count of cycles.

Systems and methods are provided for performing error recovery using LLRs generated from multi-read operations. A method may comprise selecting a set of decoding factors for a multi-read operation to read a non-volatile storage device multiple times. The set of decoding factors may include an aggregation mode for aggregating read results of multiple reads. The method may further comprise issuing a command to the non-volatile storage device to read user data according to the set of decoding factors, generating a plurality of Log-Likelihood Ratio (LLR) values using a mapping engine from a pre-selected set of LLR value magnitudes based on the set of decoding factors, obtaining an aggregated read result in accordance with the aggregation mode and obtaining an LLR value from the plurality of LLR values using the aggregated read result as an index.

Low-density parity-check (LDPC) encoded data with one or more errors is received. Information associated with an early convergence checkpoint that occurs at a fractional iteration count that is strictly greater than 0 and strictly less than 1 is received. The information associated with the early convergence checkpoint is used to perform LDPC decoding on the LDPC encoded data up to the early convergence checkpoint and generate a decoded codeword, wherein the early convergence checkpoint is prior to a first complete iteration of the LDPC decoding. At the early convergence checkpoint that occurs at the fractional iteration count, it is determined whether the LDPC decoding is successful and in the event it is determined that the LDPC decoding is successful, the decoded codeword is output.

Read data associated with Flash storage that is in a Flash storage state is received. One of a plurality of log-likelihood ratio (LLR) mapping tables is selected based at least in part on: (1) the Flash storage state and (2) a decoding attempt count associated with a finite-precision low-density parity-check (LDPC) decoder. A set of one or more LLR values is generated using the read data and the selected LLR mapping table, where each LLR value in the set of LLR values has a same finite precision as the finite-precision LDPC decoder. The finite-precision LDPC decoder generates the error-corrected read data using the set of LLR values and outputs it.