H03M13/1125

REDUCED-POWER IMPLEMENTATION OF ERROR-CORRECTION PROCESSING

A low-density parity-check (LDPC) decoder comprising a pre-processor, a core decoder, and a post-processor. The pre-processor is configured to transform a received log-likelihood-ratio (LLR) sequence into a form that enables the core decoder to toggle at a reduced rate during iterative decoding processing thereof. Upon stoppage of the decoding processing corresponding to the LLR sequence, the post-processor operates to apply a complementary transformation to the output of the core decoder, which recovers the corresponding codeword of the LDPC code. An example embodiment of the LDPC decoder operating in this manner may be able to beneficially reduce the power consumption therein by about 10%.

Systems and Methods for Decoding of Graph-Based Channel Codes Via Reinforcement Learning

Embodiments of the present disclosure relate to sequential decoding of moderate length low-density parity-check (LDPC) codes via reinforcement learning (RL). The sequential decoding scheme is modeled as a Markov decision process (MDP), and an optimized cluster scheduling policy is subsequently obtained via RL. A software agent is trained to schedule all check nodes (CNs) in a cluster, and all clusters in every iteration. A new RL state space model is provided that enables the RL-based decoder to be suitable for longer LDPC codes.

System and method for high reliability fast RAID decoding for NAND flash memories

A flash memory system may include a flash memory and a circuit for decoding a result of a read operation on the flash memory using a first codeword. The circuit may be configured to generate an estimated codeword based on a result of hard decoding the first codeword and a result of hard decoding a second codeword. The circuit may be further configured to generate soft information based on the hard decoding result of the first codeword and the estimated codeword. The circuit may be further configured to decode the result of the read operation on the flash memory using the soft information.

Integrated circuit for reception apparatus

Disclosed are an encoder, a transmission device, and an encoding method with which the transmission amount is reduced and a deterioration in transmission efficiency is suppressed while improving reception quality when QC-LDPC or a like block encoding is used. A puncture pattern setting unit (620) searches for a puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of a sub block matrix that forms a check matrix (H) of a QC-LDPC code, and a puncture unit (data reduction unit) (630) switches the puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of the sub block matrix that forms the check matrix of the QC-LDPC code.

DECODING METHOD ADOPTING ALGORITHM WITH WEIGHT-BASED ADJUSTED PARAMETERS AND DECODING SYSTEM
20220399903 · 2022-12-15 ·

A decoding method adopting an algorithm with weight-based adjusted parameters and a decoding system are provided. The decoding method is applied to a decoder. M×N low density parity check codes (LDPC codes) having N variable nodes and M check nodes are generated from input signals. In the decoding method, information of the variable nodes and the check nodes is initialized. The information passed from the variable nodes to the check nodes is formed after multiple iterations. After excluding a connection to be calculated, a product of the remaining connections between the variable nodes and the check nodes is calculated. Next, an estimated first minimum or an estimated second minimum can be calculated with multi-dimensional parameters. The information passed from the check nodes to the variable nodes can be updated for making a decision.

Application of low-density parity-check codes with codeword segmentation

A low-density parity-check (LDPC) decoder performs check node computations as N different segments of the check nodes which have connections only to a codeword segment of length C/N bits as well as check nodes that have connections across the entire codeword of length C. The decoder can include a controller or other compute hardware to decode the codeword, including to perform computations for separate segments of C/N bits of the codeword. The system can perform computations including adjustment of the decode computations based on an expected error rate for selected segments of the codeword.

Method for decoding low density parity check (LDPC)-coded signal, and terminal therefor
11595155 · 2023-02-28 · ·

Proposed is a method for a terminal to decode a signal. In particular, the method for a terminal to decode a signal comprises: a step for demodulating a first low density parity check (LDPC)-coded signal; and a step for decoding a second signal obtained from the first demodulated signal through a trained neural network. The second signal is obtained by using: an output sequence generated on the basis of the trained neural network; and a log likelihood ratio (LLR) sequence of the first signal.

ENCODING METHOD AND APPARATUS, DECODING METHOD AND APPARATUS, AND DEVICE

An encoding method and apparatus, a decoding method and apparatus, and a device are provided. The encoding method includes obtaining K to-be-encoded bits (S301), where K is a positive integer; determining a first generator matrix, where the first generator matrix includes at least two sub-blocks distributed based on a preset position relationship, and the sub-block includes a plurality of first generator matrix cores (S302); generating a second generator matrix based on the first generator matrix, where the second generator matrix includes T sub-blocks, and a position relationship between two adjacent sub-blocks of the T sub-blocks is determined based on the preset position relationship (S303), where T is a positive integer; and polar encoding the K to-be-encoded bits based on the second generator matrix (S304), to obtain encoded bits. This reduces encoding/decoding complexity.

METHOD AND APPARATUS FOR DECODING OF DATA IN COMMUNICATION AND BROADCASTING SYSTEMS
20230059393 · 2023-02-23 ·

The disclosure relates to a method performed by an apparatus for decoding an encoded signal in a communication system according to an embodiment of the disclosure may include an operation of receiving an encoded signal including a plurality of codeword bits, an operation of determining a first log-likelihood ratio (LLR) for the plurality of codeword bits, and an operation of performing iterative decoding a predetermined number of times based the first LLR, and the plurality of codeword bits may include a codeword bit included in a first subset and a codeword bit included in a second subset, and the operation of performing iterative decoding may include determining a second LLR only for the codeword bit included in the first subset of the plurality of codeword bits, and estimating, based on the second LLR, a bit value only for the codeword bit included in the first subset.

DECODING SYSTEM, AND TRANSMITTING/RECEIVING DEVICE THEREOF
20230095262 · 2023-03-30 · ·

Provided are a decoding system including a receiving device and a transmitting device. The receiving device comprises a demapper configured to convert received data into a log likelihood ratio (LLR) signal and output the LLR signal, a deparser configured to rearrange the LLR signal by deparsing the LLR signal into orthogonal frequency division multiplex (OFDM) symbols, a codeword loader configured to output the rearranged LLR signal in units of codewords, a decoder controller configured to control a maximum iteration number and the number of decoders to be enabled according to a state of the received data and a low-density parity check (LDPC) decoder configured to repeatedly decode the LLR signal in units of codewords, according to the controlled number of decoders, as many times as the controlled maximum iteration number, wherein the received data comprises real data and a packet extension corresponding to a pre-FEC (forward error correction) padding factor.