Patent classifications
H03M13/1171
Data processing device and data processing method
The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.
ITERATIVE ERROR CORRECTION IN MEMORY SYSTEMS
A system and method for detecting and correcting memory errors in CXL components is presented. The method includes receiving, into a decoder, a memory transfer block (MTB), wherein the MTB comprises data and parity information, wherein the MTB is arranged in a first dimension and a second dimension. An error checking and a correction function on the MTB is performed using a binary hamming code logic within the decoder in the first dimension. An error checking and a correction function on the MTB is performed using a non-binary hamming code logic within the decoder in the second dimension. Further, the binary hamming code logic and the non-binary hamming code logic perform the error checking on the MTB simultaneously.
Transformation of data to non-binary data for storage in non-volatile memories
A data storage system and method are provided for storing data in non-volatile memory devices. Binary data is received for storage in a non-volatile memory device. The binary data is converted into non-binary data comprising base-X values, where X is an integer greater than two. The non-binary data is encoded to generate a codeword and the codeword is written to a wordline of the non-volatile memory device.
Variable node processing methods and devices for message-passing decoding of non-binary codes
Embodiments of the invention provide a variable node processing unit for a non-binary error correcting code decoder, the variable node processing unit being configured to receive one check node message and intrinsic reliability metrics, and to generate one variable node message from auxiliary components derived from said one check node message and intrinsic reliability metrics, the intrinsic reliability metrics being derived from a received signal, an auxiliary component comprising an auxiliary symbol and an auxiliary reliability metrics associated with said auxiliary symbol, wherein the variable node processing unit comprises: a sorting and redundancy elimination unit configured to process iteratively the auxiliary components and to determine components of the variable node message by iteratively sorting the auxiliary components according to a given order of the auxiliary reliability metrics and keeping a predefined number of auxiliary components comprising the auxiliary symbols that are the most reliable and all different from one another.
Forward error correction using non-binary low density parity check codes
Methods, systems and devices for forward error correction in orthogonal time frequency space (OTFS) communication systems using non-binary low-density parity-check (NB-LDPC) codes are described. One exemplary method for forward error correction includes receiving data, encoding the data via a non-binary low density parity check (NB-LDPC) code, wherein the NB-LDPC code is characterized by a matrix with binary and non-binary entries, modulating the encoded data to generate a signal, and transmitting the signal. Another exemplary method for forward error correction includes receiving a signal, demodulating the received signal to produce data, decoding the data via a NB-LDPC code, wherein the NB-LDPC code is characterized by a matrix with binary and non-binary entries, and providing the decoded data to a data sink.
Method and device for decoding data stored in a DNA-based storage system
A method includes obtaining, for each type of nucleotide, a probability density function, the probability density functions being obtained from measurements of current drops produced during at least one passage of at least one sequence of reference nucleotides through a nanopore sequencer; obtaining measurements of current drops produced when the sequence of nucleotides to be decoded passes through the nanopore sequencer; calculating, for each measurement value considered and for each type of nucleotide of the B types of nucleotides, a piece of reliability information based on the probability density function obtained for the type of nucleotide considered; obtaining a decoded value identifying a type of nucleotide from the B types of DNA nucleotides, by applying a soft decoding algorithm with an error correction code to the current drop measurement and to the B pieces of reliability information obtained for the considered measurement value.
METHODS AND DEVICES FOR ERROR CORRECTING CODES DECODING
Embodiments of the invention provide a check node processing unit implemented in a decoder, said decoder being configured to decode a signal encoded using an error correcting code, said signal comprising symbols, the check node processing unit being configured to receive at least two input messages and to generate at least one output message, each message comprising a plurality of components, each component comprising a value of a symbol and a reliability metrics associated with said symbol, wherein the check node processing unit comprises: a data structure (31) configured to store said input messages, the components of the input messages being associated with an integer index in the data structure; a data processing unit (33) configured to apply one or more iterations of a transformation operation to at least a part of the data structure, each iteration of the transformation operation being performed to arrange the components of said input messages in said data structure (31) depending on at least some of the components of the messages associated with a given value of the integer index, which provides a transformed data structure; a calculation unit (35) configured to determine said at least one output message from the components comprised in said transformed data structure.
LDPC encoding for memory cells with arbitrary number of levels
The present disclosure generally relates to applying LDPC coding to memory cells with an arbitrary number of levels. Modulation code is applied to a first portion of user bits. The coded user data is stored in a first modulation block. Parity bits are then generated for the first portion of user bits. The parity bits are then stored in a second modulation block different from the first modulation block. Modulation code is then applied to a second portion of user bits which are stored in the second modulation block. Parity bits are then generated for the second portion of user bits and stored in a third modulation block. The parity bits are thus embedded in a separate modulation block from the modulation block where the user data is stored.
Apparatus and method for transmitting and receiving a quasi-cyclic low density parity check code in a multimedia communication system
A method and apparatus are provided for transmitting an LDPC code in a multimedia system. The method includes generating an LDPC code based on a resulting parity check matrix which is generated by performing a row splitting operation on a base parity check matrix; and transmitting the LDPC code. The row splitting operation includes splitting each row block included in the base parity check matrix into row blocks, a number of the row blocks is determined based on a splitting factor, and the splitting factor is determined based on a number of repair symbols included in a repair symbol block of the base parity check matrix, a number of rows included in the base parity check matrix, and a scaling factor for determining a size of each permutation matrix in the resulting parity check matrix and a size of each zero matrix included in the resulting parity check matrix.
METHOD AND APPARATUS FOR SHORTENING AND PUNCTURING NON-BINARY CODE
The present disclosure relates to a pre-5.sup.th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). The present invention relates to a method and a device for efficiently shortening and puncturing a non-binary LDPC code, the method for a transmitter shortening and puncturing a non-binary code being capable of supporting various modulation methods by using a single non-binary code, and the method comprising the steps of: shortening, on the basis of a modulation method, at least one information bit in at least one information symbol constituting the non-binary code; encoding the at least one information symbol having a shortened information bit; and puncturing, on the basis of the modulation method, at least one parity code in at least one parity symbol obtained through the encoding step.