A decompression apparatus is provided. The decompression apparatus includes a memory configured to store compressed data decompressed and used in neural network processing of an artificial intelligence model, a decoder configured to include a plurality of logic circuits related to a compression method of the compressed data, decompress the compressed data through the plurality of logic circuits based on an input of the compressed data, and output the decompressed data, and a processor configured to obtain data of a neural network processible form from the data output from the decoder.

The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 13/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.

The present disclosure provides techniques for bandwidth constrained communication systems with frequency domain information processing. A bandwidth constrained equalized transport (BCET) communication system can include a transmitter, a communication channel, and a receiver. The transmitter can include a pulse-shaping filter that intentionally introduces memory into a signal in the form of inter-symbol interference, an error control code (ECC) encoder, a multidimensional fast Fourier transform (FFT) processing block that processes the signal in the frequency domain, and a first interleaver. The receiver can include an information-retrieving equalizer, a deinterleaver with an ECC decoder, and a second interleaver joined in an iterative ECC decoding loop. The communication system can be bandwidth constrained, and the signal can comprise an information rate that is higher than that of a communication system without intentional introduction of the memory at the transmitter.

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to create a dual parity matrix. The dual parity matrix includes a full parity form that includes a payload, a first parity portion, and a second parity portion and a reduced parity form that includes the payload and the first parity portion. The second parity portion is 0. The controller is further configured to create an incremental parity construction matrix. The incremental parity construction matrix includes two arrays. A first array includes a first payload portion, a first, first parity portion, and a first, second parity portion and a second array includes a second payload portion, a second, first parity portion, and a second, second parity portion. The incremental parity construction matrix is arranged in either a block triangular construction or a block diagonal construction.

The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 10/15 or 12/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.

An encoding method and apparatus, a decoding method and apparatus, and a device are provided. The encoding method includes obtaining K to-be-encoded bits (S301), where K is a positive integer; determining a first generator matrix, where the first generator matrix includes at least two sub-blocks distributed based on a preset position relationship, and the sub-block includes a plurality of first generator matrix cores (S302); generating a second generator matrix based on the first generator matrix, where the second generator matrix includes T sub-blocks, and a position relationship between two adjacent sub-blocks of the T sub-blocks is determined based on the preset position relationship (S303), where T is a positive integer; and polar encoding the K to-be-encoded bits based on the second generator matrix (S304), to obtain encoded bits. This reduces encoding/decoding complexity.

An LDPC code encoding method and a communication apparatus are described that provide increased redundant bits through retransmission in an IR-HARQ mechanism, so as to decrease a channel coding rate, and improve decoding performance of an LDPC code. A check matrix of the LDPC code is used as a basic matrix, and the basic matrix is extended to obtain a mother matrix compatible with a plurality of code rates. During LDPC encoding, a transmit device reads, from the mother matrix, a check matrix corresponding to a required code rate, and performs LDPC encoding on an information bit sequence based on the read check matrix. LDPC encoding is performed on the information bit sequence by using check matrices of different sizes, to obtain different quantities of redundant bits.

Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.

This application provides a communication method and apparatus. The method includes: encoding a to-be-transmitted first bit sequence to obtain a first matrix, where the first matrix includes a plurality of bit square matrices of a same size, and each bit square matrix includes a plurality of pieces of bit data; performing, based on a first mapping relationship, position transformation in a range of each bit square matrix on the bit data of each bit square matrix in the first matrix, to obtain a second matrix after the position transformation; and performing bit data position transformation among bit square matrices on the second matrix to obtain a third matrix, and modulating a to-be-sent first symbol sequence based on the third matrix.

An electronic device, configured to perform a series of low-density parity check, LDPC, decoding operations for a parity check matrix, PCM, derived from at least one basegraph having a plurality of rows, includes: two or more check node, CN, sub-processors having input-output (I-O) port(s); and a controller configured to activate a subset of the I-O port(s) based on a current LDPC decoding sub-step of the LDPC decoding operations and the basegraph. The CN sub-processors support: a first single LDPC decoding operation to perform LDPC decoding computations for two or more rows of the PCM that are derived from different orthogonal rows of the plurality of rows in the basegraph; and a second mode whereby two or more of CN sub-processors co-operate to perform LDPC decoding computations for two or more rows of the PCM that are derived from a single row in the basegraph.