Methods, systems, and computer-readable storage media for receiving, by an anomalous operation detection service, current signal data representing a driving current applied to a device over a time period, processing, by an anomalous operation detection service, the current signal data through a deep neural network (DNN) module, a frequency spectrum analysis (FSA) module, and a time series classifier (TSC) module to provide a set of indications, each indication in the set of indications indicating one of normal operation of the device and anomalous operation of the device, processing, by an anomalous operation detection service, the set of indications through a voting gate to provide an output indication, the output indication indicating one of normal operation of the device and anomalous operation of the device, and selectively transmitting one or more of an alert and a message based on the output indication.

Hierarchical coding architectures and schemes based on multistage concatenated codes are described. For instance, multiple encoder and decoder hierarchies may be implemented along with use of corresponding stages of concatenated codes. The coding scheme generally includes an inner coding scheme (e.g., a polar coding scheme, such as a hybrid polar code or Bose Chaudhuri and Hocquenghem (BCH) code), an outer coding scheme (e.g., a Reed-Solomon (RS) coding scheme), and one or more middle coding schemes. The inner coding scheme is based on a polarization transformation (e.g., polar codes with cyclic redundancy check (CRC) codes, polar codes with dynamic freezing codes, polarization-adjusted convolutional (PAC) codes, etc.) which allows for embedding parity data from an outer code inside a codeword along with the user data. The outer coding scheme has a similar concatenated structure (e.g., of an inner RS code with an outer RS code).

A method for execution by a dispersed storage network (DSN) managing unit includes receiving access information from a plurality of distributed storage and task (DST) processing units via a network. Cache memory utilization data is generated based on the access information. Configuration instructions are generated for transmission via the network to the plurality of DST processing units based on the cache memory utilization data.

An operating method of a memory device includes storing position information regarding a codeword including an erasure and erasure information including position information regarding the erasure in a memory region, loading the position information regarding the codeword to a row decoder and a column decoder, determining whether a read address corresponding to a read instruction is identical to the position information regarding the codeword including the erasure, in response to the read instruction from a host, transmitting the position information of the erasure to an error correction code (ECC) decoder, when the read address is identical to the position information regarding the codeword including the erasure, and correcting, by the ECC decoder, an error in a codeword received from a memory cell array using the position information regarding the erasure.

Techniques for using erasure coding in a single region to reduce the likelihood of losing objects in a cloud object storage platform are provided. In one set of embodiments, a computer system can upload a plurality of data objects to a region of a cloud object storage platform, where the plurality of data objects including modifications to a data set. The computer system can further compute a parity object based on the plurality of data objects, where the parity object encodes parity information for the plurality of data objects. The computer system can then upload the parity object to the same region where the plurality of data objects was uploaded.

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to perform by group-wise interleaving a plurality of bit groups configuring the parity bits based on a group-wise interleaving pattern comprising a first pattern and a second pattern; a puncturer configured to puncture some of the parity-permutated parity bits; and an additional parity generator configured to select at least some of the punctured parity bits to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern.

The present invention relates to a digital broadcasting system for transmitting/receiving a digital broadcasting signal and a method of processing data. In one aspect of the present invention provides a method of processing data, the method including receiving a broadcasting signal in which mobile service data and main service data are multiplexed, demodulating the received broadcasting signal, obtaining an identifier indicating that data frame of the broadcasting signal includes service guide information, decoding and storing the service guide information from the data frame; and outputting a service included in the mobile service data according to the decoded service guide information.

A syndrome calculation circuit includes a matrix product calculation circuit. The matrix product calculation circuit is configured to generate syndrome bits in a composite field by calculating a matrix product of input data bits and a first arithmetic matrix. The first arithmetic matrix is a matrix product of a basis conversion matrix for converting a data string from a Galois field to the composite field and a second arithmetic matrix, which is at least a part of a parity check matrix.

A memory device having a Low-Density Parity-Check (LDPC) decoder that is energy efficient and has a low error floor. The decoder is configured to determine syndromes of bits in a codeword, select bits in the codeword based at least in part on the syndromes according to a first mode, and flip the selected bits in the codeword. The decoder can repeat the bit selection and flipping operations to iteratively improve the codeword and reduce parity violations. Further, the decoder can detect a pattern in parity violations of the codeword in its iterative bit flipping operations. In response, the decoder can change from the first mode to a second mode in bit selection for flipping. For example, the decoder can transmit from a dynamic syndrome mode to a static syndrome mode in response to the pattern of repeating a cycle of bit flipping iterations.

A decoding apparatus includes input circuitry configured to receive coded data; and decoding circuitry configured to decode the coded data to obtain decoded data. The coded data are generated by using an encoding process at an encoding apparatus. The encoding process includes: (i) repeatedly collecting first data blocks included in the decoded data to generate at least one second data block; (ii) dividing at least one third data block included in the decoded data into fourth data blocks; (iii) allocating fifth data blocks included in the decoded data to respective sixth data blocks without collecting the first data blocks or dividing the at least one third data block; and (iv) performing an error correcting encoding on the at least one second data block, the fourth data blocks, and the sixth data blocks in accordance with a coding rate selected from a plurality of coding rates to generate parity data.