An information processing apparatus includes: a decoding module, configured to receive M first codewords from at least one peer device, where each first codeword includes first service data with a K-unit length and an error correction code with an R-unit length, where the decoding module is further configured to decode the M first codewords to obtain M second codewords, where a length of each second codeword is a sum of the K-unit length and the R-unit length, each second codeword includes second service data with the K-unit length and error correction information, the second service data is error-corrected first service data; and a classification and statistics collection module, configured to determine a bit error rate of the first service data based on the error correction information.

An information processing apparatus includes: a decoding module, configured to receive M first codewords from at least one peer device, where each first codeword includes first service data with a K-unit length and an error correction code with an R-unit length, where the decoding module is further configured to decode the M first codewords to obtain M second codewords, where a length of each second codeword is a sum of the K-unit length and the R-unit length, each second codeword includes second service data with the K-unit length and error correction information, the second service data is error-corrected first service data; and a classification and statistics collection module, configured to determine a bit error rate of the first service data based on the error correction information.

This document discloses techniques, apparatuses, and systems for sparse encodings for control signals. Integrated circuits (ICs) may transmit various signals to manage interactions between circuit components of the IC. These critical signals are common targets for malicious attacks because, when altered, they can cause the IC to perform differently than is intended, and in some cases, bypass security measures. To protect against these attacks, the sparse encodings for control signals described herein transmit critical signals with sparse encodings. Further, multiple rails may be used to transmit a single bit of the sparsely encoded critical signals across each rail. In this way, the techniques described herein may provide a scalable solution that may be adjusted differently based on each implementation.

A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.

A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.

An error correction circuit includes: a first error correction encoder for generating a plurality of row-codewords by performing first error correction encoding on each of a plurality of messages; a second error correction encoder for generating a plurality of column-codewords; a first error correction decoder for performing first error correction decoding on each of read row-vectors corresponding to the plurality of row-codewords, and outputting a soft information of the first error correction decoding; and a second error correction decoder for determining whether each of m-bit symbols in read column-vectors corresponding to the column-codewords is reliable, based on the soft information corresponding to each of the p-bit symbols, and performing second error correction decoding on the read column-vectors, based on the determination of whether each of the m-bit symbols is reliable.

An error correction circuit includes: a first error correction encoder for generating a plurality of row-codewords by performing first error correction encoding on each of a plurality of messages; a second error correction encoder for generating a plurality of column-codewords; a first error correction decoder for performing first error correction decoding on each of read row-vectors corresponding to the plurality of row-codewords, and outputting a soft information of the first error correction decoding; and a second error correction decoder for determining whether each of m-bit symbols in read column-vectors corresponding to the column-codewords is reliable, based on the soft information corresponding to each of the p-bit symbols, and performing second error correction decoding on the read column-vectors, based on the determination of whether each of the m-bit symbols is reliable.

A data processing system having a neural network architecture for receiving a binary network input and, in dependence on the binary network input, propagating signals via a plurality of processing nodes, in accordance with respective binary weights, to form a network output, the data processing system being configured to train a node by implementing an error correcting function to identify a set of binary weights which minimize, for a given input to the node, any error between an output of the node when formed in accordance with current binary weights of the node and a preferred output from the node and to update the binary weights of the node to be the identified weights. This training is performed without storing and/or using any higher arithmetic precision weights or other components.

The current invention relates to an encoder for converting a set of data words into a data block having a header section, a checksum section and a payload section; the encoder comprising: a header inserter arranged to insert a header pattern in the data block; a checksum calculator arranged to calculate a checksum of the set of data words; a data word converter arranged to convert the set of data words into a set of obfuscated data words being a result of applying an exclusive or operation between the set of data words and the checksum.

The current invention relates to an encoder for converting a set of data words into a data block having a header section, a checksum section and a payload section; the encoder comprising: a header inserter arranged to insert a header pattern in the data block; a checksum calculator arranged to calculate a checksum of the set of data words; a data word converter arranged to convert the set of data words into a set of obfuscated data words being a result of applying an exclusive or operation between the set of data words and the checksum.