Hierarchical coding architectures and schemes based on multistage concatenated codes are described. For instance, multiple encoder and decoder hierarchies may be implemented along with use of corresponding stages of concatenated codes. The coding scheme generally includes an inner coding scheme (e.g., a polar coding scheme, such as a hybrid polar code or Bose Chaudhuri and Hocquenghem (BCH) code), an outer coding scheme (e.g., a Reed-Solomon (RS) coding scheme), and one or more middle coding schemes. The inner coding scheme is based on a polarization transformation (e.g., polar codes with cyclic redundancy check (CRC) codes, polar codes with dynamic freezing codes, polarization-adjusted convolutional (PAC) codes, etc.) which allows for embedding parity data from an outer code inside a codeword along with the user data. The outer coding scheme has a similar concatenated structure (e.g., of an inner RS code with an outer RS code).

Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.

Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.

Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.

In one embodiment, an apparatus for decoding is disclosed. The apparatus includes a memory and at least one processor coupled to the memory. The at least one processor is configured to obtain one or more parameters corresponding to a system, determine a plurality of settings corresponding to an adaptive soft decoding procedure for decoding a product code, wherein the plurality of settings are determined based on the one or more parameters using a trellis, and determine a decoded codeword by performing the adaptive soft decoding procedure on the received codeword, wherein the adaptive soft decoder utilizes the determined plurality of settings.

Techniques are described for decoding a codeword. In one example, the techniques include obtaining a first message comprising reliability information corresponding to each bit in the first codeword, determining a plurality of least reliable bits in the first codeword, and generating a plurality of flipped messages by flipping one or more of the plurality of least reliable bits in the first codeword. A number of the plurality of least reliable bits is equal to a first parameter and a number of flipped bits in each of the plurality of flipped messages is less than or equal to a second parameter. The method further includes decoding one or more of the plurality of flipped messages using a hard decoder to generate one or more candidate codewords.

An apparatus for decoding a TPC codeword is disclosed. The apparatus includes a memory and a processor coupled to the memory. The processor is configured to receive a first set of soft information corresponding to the TPC codeword. The TPC codeword includes at least one codeword corresponding to each of first, second, and third dimensions. The processor is further configured to iteratively perform a first soft decoding procedure on the at least one codeword corresponding to the first dimension to generate a first candidate codeword and upon determining that the first candidate codeword is not a correct codeword, and perform a second decoding procedure on the at least one codeword corresponding to the third dimension to generate a second candidate codeword. The second decoding procedure generates a second set of soft information to be used at a later iteration of the first decoding procedure.

Apparatuses and methods for data storage error protection are described. One example apparatus for data storage error protection includes an array of memory cells arranged in a first dimension and a second dimension. A controller is configured to determine a set of symbols corresponding to data stored in the memory cells. The controller is configured to add subsets of the set of symbols obliquely oriented to the first dimension and the second dimension to determine a number of parity check symbols. The controller is configured to use a same number of parity check symbols for protection of a first subset of memory cells oriented parallel to the first dimension as used for protection of a second subset of memory cells oriented parallel to the second dimension.

Methods, apparatus, systems, architectures and interfaces for encoding/decoding a QD-DTS-PrCC are provided. The decoding method includes determining a number k.sub.TS of input bits included in a transmission of a data stream and a first bit of the input bits included in the transmission in the data stream; determining a number of Encoded Bit Blocks (EBBs), each of the EBBs including any number of data blocks that are previously transmitted Transmit Segments (TS) of the data stream, each of the data blocks having a bit length of k.sub.TS bits; selecting that number of EBBs for encoding a QD-DTS-PrCC component codeword (QDCC) of the transmission according to a DTS indexing method for indexing a plurality of EBBs; generating the QDCC including a TS, Virtual Segments (VSs), and r.sub.c parity bits, a dimensionality of the QD-DTS-PrCC being at least 2; and extracting the calculated TS of the QDCC to an output EBB.

Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.