H03M13/2945

DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA

The present invention relates to a digital broadcasting system for transmitting/receiving a digital broadcasting signal and a method of processing data. In one aspect of the present invention provides a method of processing data, the method including receiving a broadcasting signal in which mobile service data and main service data are multiplexed, demodulating the received broadcasting signal, obtaining an identifier indicating that data frame of the broadcasting signal includes service guide information, decoding and storing the service guide information from the data frame; and outputting a service included in the mobile service data according to the decoded service guide information.

CIRCUIT AND METHOD FOR IMPRINT REDUCTION IN FRAM MEMORIES
20180012642 · 2018-01-11 ·

Disclosed embodiments include a memory device having a memory array that includes a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line and a sense amplifier that includes first and second transistors arranged in a cross-coupled configuration with third and fourth transistors, the first and second transistors being of a first conductivity type and the third and fourth transistors being of a second conductivity type, a first inverter having an input coupled to a first common drain terminal of the first and third transistors and an output coupled to the first bit line, and a second inverter having an input coupled to a second common drain terminal of the second and fourth transistors and an output coupled to the second bit line.

DEVICE AND METHOD FOR EFFICIENTLY ENCODING QUASI-CYCLIC LDPC CODES
20230231576 · 2023-07-20 ·

A data encoding device suitable for encoding a plurality of LDPC codes is disclosed including an input interface and an output interface, and a first circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of a first multiplexer circuit, a second circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of the first multiplexer circuit, a third circuit for encoding quasi-cyclic LDPC code, connected at an input to the output of the first multiplexer circuit and at an output to the input of a second multiplexer circuit.

SPATIALLY COUPLED FORWARD ERROR CORRECTION ENCODING METHOD AND DEVICE USING GENERALIZED ERROR LOCATING CODES AS COMPONENT CODES

The present disclosure provides an encoding and decoding device implementing an improved forward error correction (FEC) coding/decoding method. In particular, the encoding device is configured to encode a stream of data symbols using a spatially coupled code (e.g. staircase codes, braided block codes or continuously interleaved block codes), wherein at least one generalized error location (GEL) code is used as a component code of the spatially coupled code. Accordingly, the decoding device is configured to decode a sequence of encoded symbol blocks using a spatially coupled code, wherein at least one GEL code is used as a component code of the spatially coupled code. Thereby, a suitable spatially coupled FEC code that allows for very low-latency, high-throughput, high-rate applications with a low-complexity decoding procedure, and allows for mitigation of the error-floor, is designed.

Circuit and method for imprint reduction in FRAM memories

A method of operating a memory circuit (FIGS. 8A and 8B) is disclosed. The method includes writing true data (01) to a plurality of bits (B.sub.0, B.sub.1). A first data state (0) is written to a signal bit (B.sub.i) indicating the true data. The true data is read and complementary data (10) is written to the plurality of bits. A second data state (1) is written to the signal bit indicating the complementary data.

Error correction code (ECC) operations in memory for providing redundant error correction

Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.

Digital broadcasting system and method of processing data

The present invention relates to a digital broadcasting system for transmitting/receiving a digital broadcasting signal and a method of processing data. In one aspect of the present invention provides a method of processing data, the method including receiving a broadcasting signal in which mobile service data and main service data are multiplexed, demodulating the received broadcasting signal, obtaining an identifier indicating that data frame of the broadcasting signal includes service guide information, decoding and storing the service guide information from the data frame; and outputting a service included in the mobile service data according to the decoded service guide information.

Partial reverse concatenation for data storage devices using composite codes

In one embodiment, a system includes a processor, and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor. The logic is configured to cause the processor to write, by the processor, data to a storage medium of a data storage system using a partial reverse concatenated modulation code. The partial reverse concatenated modulation code comprises encoding the data by applying a C2 encoding scheme prior to encoding the data by applying one or more modulation encoding schemes, followed by encoding the data by applying a C1 encoding scheme subsequent to the encoding of the data with the one or more modulation encoding schemes.

Coding device, transmitter, decoding device, and receiver

In a coding device (20), a first coding unit (21) generates a parity of an RS code by coding, based on the RS code, each first data sequence existing in a direction different from a row direction of input data, and generates coded data by attaching the parity of the RS code to each first data sequence, thereby consequently expanding a matrix. A second coding unit (22) generates a parity of a BCH code and a parity of an LDPC code by coding, based on the BCH code and the LDPC code, each second data sequence existing in a row direction of the coded data, and generates a plurality of DVB-S2 frames (13) including, per DVB-S2 frame (13), one data sequence existing in the row direction of the coded data, the corresponding parity of the BCH code, and the corresponding parity of the LDPC code.

Memory system, packet protection circuit, and CRC calculation method

A memory system includes a packet protection circuit. The packet protection circuit includes a plurality of first CRC calculation circuits, each configured to calculate a CRC of M-byte data, where M is an integer greater than or equal to 1 and less than N, where N is an integer greater than or equal to 2, a first selector configured to output a CRC calculation result of one of the first CRC calculation circuits, and a second CRC calculation circuit configured to calculate a CRC of L-byte data, where L<N, where L=N×Z, and Z is an integer greater than 1, and add the CRC of L-byte data to the CRC calculation result output from the first selector to generate a first CRC that is compared with a second CRC to detect an error in a data packet transmitted between the host interface unit and the host device.