A memory controller includes an interface and a processor. The interface communicates with a plurality of memory cells, and an individual one of the plurality of memory cells stores data in multiple predefined programming levels. The processor is configured to read an Error Correction Code (ECC) code word from a group of memory cells, via the interface, using multiple read thresholds positioned between adjacent programming levels, for producing multiple readouts that contain respective numbers of errors, to derive from the code word a reference readout that contains no errors, or contains a number of errors smaller than in the code word, to calculate multiple distances between the reference readout and the respective readouts, and set a preferred read threshold based on the calculated distances, and to perform subsequent read operations for retrieving data from the plurality of memory cells, using the preferred read threshold.

A method for decoding a signal encoded with polar codes by a decoding system is provided. The method comprises receiving, from a transmission system, a signal in which a plurality of cyclic redundancy checks (CRCs) are encoded by the polar codes, the plurality of CRCs being inserted into positions determined based on a plurality of information bits, a number of the plurality of information bits and a total code length, and decoding a code section including bits ranging from a first bit of the signal to a position where a last bit of a first CRC is inserted. The method further comprises re-performing successive cancellation flip decoding for the decoded code section, or determining whether to decode a next code section adjacent to the decoded code section, based on whether a CRC is detected in the decoded code section.

A method includes calculating a number of iterative detection and decoding (IDD) iterations and a number of decoding iterations for each of a plurality of channel coding units in a target codeword; calculating a demodulation time and a decoding time for the target codeword based on the number of IDD iterations and the number of decoding iterations for the target codeword; adding the target codeword to a codeword set, based on a demodulation time and a decoding time for codewords in the codeword set and the target codeword; and performing an IDD operation based on a number of IDD iterations and a number of decoding iterations.

A method of responding to a read request from a host includes: obtaining read data from a memory device, performing first iteration ECC decoding on the read data to generate a plurality of pieces of decoded data, selecting one of the plurality of pieces of decoded data as intermediate data as intermediate data, generating preprocessed data based on the read data and the intermediate data and performing second iteration ECC decoding on the preprocessed data when the first iteration ECC decoding fails, and outputting the intermediate data to the host when the first iteration ECC decoding succeeds.

Methods, systems, and apparatuses for stall mitigation in iterative decoders are described. A codeword is received from a memory device. The codeword is iteratively error corrected based on a first bit flipping criterion. A stall condition in the multiple error correction iterations is detected. In response to the detection, the codeword is error corrected based on a second bit flipping criterion that is different from the first bit flipping criterion.

In data communications, a suitably designed contrast coding scheme, comprising a process of contrast encoding (108) at a transmitter end (101) and a process of contrast decoding (120) at a receiver end (103), may be used to create contrast between the bit error rates ‘BERs’ experienced by different classes of bits. Contrast coding may be used to tune the BERs experienced by different subsets of bits, relative to each other, to better match a plurality of forward error correction ‘FEC’ schemes (104, 124) used for transmission of information bits (102), which may ultimately provide a communications system (100) having a higher noise tolerance, or greater data capacity, or smaller size, or lower heat.

Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose-Chaudhuri-Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose-Chaudhuri-Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.

Example systems, read channel circuits, data storage devices, and methods to provide signal correction based on soft information in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector, and a signal correction circuit. The soft output detector passes detected data bits and corresponding soft information to the signal correction circuit. The signal correction circuit uses the soft information to determine a signal correction value, which is combined with input signal to return a corrected signal to the soft output detector for a next iteration. In some configurations, the signal correction value may compensate for DC offset, AC coupling poles, and/or signal asymmetries to reduce baseline wander in the read channel.

An operation method of a receiving node may include performing a decoding operation for calculating first and second output transform values corresponding to first and second unit output nodes in each of a plurality of operation units constituting the polar decoder, based on first and second input transform values corresponding to first and second unit input nodes, and the decoding operation may include setting initial values of first and second variables for calculating the first output transform value; performing an iterative loop operation for updating the first and second variables; and calculating the first output transform value based on values of the first and second variables updated until a time when the iterative loop operation is terminated, wherein the iterative loop operation is terminated without performing iterations in which the first and second variables are determined not to be updated among a plurality of iterations.

Methods, systems, and apparatuses for stall mitigation in iterative decoders are described. A codeword is received from a memory device. The codeword is iteratively error corrected based on a first bit flipping criterion. A stall condition in the multiple error correction iterations is detected. In response to the detection, the codeword is error corrected based on a second bit flipping criterion that is different from the first bit flipping criterion.