A decoding device includes a controller classifying a bitstream as a first bitstream and a second bitstream based on a plurality of blocks defined by a matrix and included in a frame, a first decoder including a first processor performing decoding on the first bitstream and outputting first decoding data and a first memory, a second decoder including a second processor performing decoding on the second bitstream and outputting second decoding data and a second memory, a first buffer transmitting the first decoding data to the second memory, and a second buffer transmitting the second decoding data to the first memory. The first processor controls the second memory to store the first decoding data, and the second processor controls the first memory to store the second decoding data.

A memory device having a Low-Density Parity-Check (LDPC) decoder that is energy efficient and has a low error floor. The decoder is configured to determine syndromes of bits in a codeword, select bits in the codeword based at least in part on the syndromes according to a first mode, and flip the selected bits in the codeword. The decoder can repeat the bit selection and flipping operations to iteratively improve the codeword and reduce parity violations. Further, the decoder can detect a pattern in parity violations of the codeword in its iterative bit flipping operations. In response, the decoder can change from the first mode to a second mode in bit selection for flipping. For example, the decoder can transmit from a dynamic syndrome mode to a static syndrome mode in response to the pattern of repeating a cycle of bit flipping iterations.

Example systems, read channel circuits, data storage devices, and methods to provide signal correction based on soft information in a read channel are described. The read channel circuit includes a soft output detector, such as a soft output Viterbi algorithm (SOVA) detector, and a signal correction circuit. The soft output detector passes detected data bits and corresponding soft information to the signal correction circuit. The signal correction circuit uses the soft information to determine a signal correction value, which is combined with input signal to return a corrected signal to the soft output detector for a next iteration. In some configurations, the signal correction value may compensate for DC offset, AC coupling poles, and/or signal asymmetries to reduce baseline wander in the read channel.

A set of bits of a segment of a memory device that is associated with an unsuccessful first decoding operation can be identified. A discrepancy value for at least one bit of the set of bits can be calculated. It can be determined whether the discrepancy value calculated for the at least one bit of the set of bits corresponds to a correction capability of the failed decoding operation. In response to determining that the discrepancy value calculated for the at least one bit corresponds to the correction capability of the failed decoding operation, the at least one bit of the set of bits can be corrected by switching a value of the at least one bit.

Provided is an error correction decoding device including an inner code iterative decoding circuit, a parameter generation circuit, and a first control circuit. The first control circuit is configured to: receive, as parameters, a threshold and a maximum iteration count which are generated by the parameter generation circuit; and compare, when an iteration count does not reach the maximum iteration count, a non-zero-value count sequentially output from the inner code iterative decoding circuit and the threshold set for each iteration count, and stop an iterative operation by the inner code iterative decoding circuit when a result of the comparison satisfies a stopping condition set in advance.

Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose—Chaudhuri—Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose—Chaudhuri—Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.

A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.

The present disclosure provides an encoding and decoding device implementing an improved forward error correction (FEC) coding/decoding method. In particular, the encoding device is configured to encode a stream of data symbols using a spatially coupled code (e.g. staircase codes, braided block codes or continuously interleaved block codes), wherein at least one generalized error location (GEL) code is used as a component code of the spatially coupled code. Accordingly, the decoding device is configured to decode a sequence of encoded symbol blocks using a spatially coupled code, wherein at least one GEL code is used as a component code of the spatially coupled code. Thereby, a suitable spatially coupled FEC code that allows for very low-latency, high-throughput, high-rate applications with a low-complexity decoding procedure, and allows for mitigation of the error-floor, is designed.

A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.

Provided are a decoding system including a receiving device and a transmitting device. The receiving device comprises a demapper configured to convert received data into a log likelihood ratio (LLR) signal and output the LLR signal, a deparser configured to rearrange the LLR signal by deparsing the LLR signal into orthogonal frequency division multiplex (OFDM) symbols, a codeword loader configured to output the rearranged LLR signal in units of codewords, a decoder controller configured to control a maximum iteration number and the number of decoders to be enabled according to a state of the received data and a low-density parity check (LDPC) decoder configured to repeatedly decode the LLR signal in units of codewords, according to the controlled number of decoders, as many times as the controlled maximum iteration number, wherein the received data comprises real data and a packet extension corresponding to a pre-FEC (forward error correction) padding factor.