A method and a decoder for receiving a message encoded in Turbo Codes and modulated for transmission as an analog signal includes: (a) demodulating the analog signal to recover the Turbo Codes; and (b) decoding the Turbo Codes to recover the message using an iterative Turbo Code decoder, wherein the decoding includes performing an error detection after a predetermined number of iterations of the Turbo Code decoder to determine whether or not an error has occurred during the transmission. The predetermined number of iterations may be, for example, two. Depending on the result of the error detection, the decoding may stop, a request for retransmission of the message may be sent, or further iterations of decoding in the Turbo Code decoder may be carried out.

A decoding method and device for Turbo product codes, a decoding device, a decoder and a computer storage medium are provided. The method includes: a received codeword of a Turbo product code is acquired, and iterative decoding is performed on the received codeword for a set first iterative decoding times (S101); a decoding result of iterative decoding performed for the first iteration times is judged according to a first decoding rule to obtain a decoding identifier representing the decoding result (S102); and error correction processing is performed on the Turbo product code on which iterative decoding is performed for the first iteration times according to the decoding identifier (S103).

A method, apparatus and system for feeding back early stop decoding are provided. The method includes: a terminal side adjusting encoded TFCI bits, and sending the adjusted TFCI bits to a NodeB side via a TFCI domain of an uplink DPCCH (S302); after sending the adjusted TFCI bits to the NodeB side, the terminal side performing a decoding operation on a downlink DPCH, and feeding back, via an idle TFCI domain of the uplink DPCCH, a decoding result to the NodeB side (304). By applying the technical solution, at least one of the problems in the related art that a NodeB cannot obtain a TFCI in time and a terminal side cannot feed back a downlink decoding result in time during early stop decoding can be solved.

Memory controllers, decoders and methods to selectively perform bit-flipping (BF) decoding and min-sum (MS) decoding on codewords of an irregular low-density parity-check (LDPC) code. Bit-flipping (BF) decoding is executed with respect to variable nodes having relatively high column weights. MS decoding is executed with respect to variable nodes having relatively low column weights. A column-weight threshold is used to group the variable nodes into the higher and lower column weight groups. The two decoding techniques exchange results during the overall decoding process.

Embodiments herein provide a method for predicting iterations for decoding an encoded data at an electronic device. The method includes: receiving, by the electronic device, the encoded data; detecting, by the electronic device, signal parameters associated with the encoded data; predicting, by the electronic device, one of a cyclic redundancy check (CRC) failure, CRC success, and a CRC uncertainty in iterations for decoding the encoded data based on the signal parameters using a Neural Network (NN) model.

This invention presents a method and apparatus for vertical layered finite alphabet iterative decoding of low-density parity-check codes (LDPC) which operate on parity check matrices that consist of blocks of sub-matrices. The iterative decoding involves passing messages between variable nodes and check nodes of the Tanner graph that associated with one or more sub-matrices constitute decoding blocks, and the messages belong to a finite alphabet. Various embodiments for the method and apparatus of the invention are presented that can achieve very high throughputs with low hardware resource usage and power.

A decoding method and device for Turbo product codes, a decoding device, a decoder and a computer storage medium are provided. The method includes: a received codeword of a Turbo product code is acquired, and iterative decoding is performed on the received codeword for a set first iterative decoding times (S101); a decoding result of iterative decoding performed for the first iteration times is judged according to a first decoding rule to obtain a decoding identifier representing the decoding result (S102); and error correction processing is performed on the Turbo product code on which iterative decoding is performed for the first iteration times according to the decoding identifier (S103).

A data decoder includes a communication unit receiving a bit signal with encoded data; a first operation unit that bit shifts the bit signal by a first length, corresponding to a length of a spreading code used to encode the data, to generate a first operation stream; a second operation unit generating a second operation stream without the spreading code; a third operation unit that bit shifts the second operation stream by a second length to generate a third operation stream; a fourth operation unit generating a fourth operation stream from which the data is removed using the second operation stream and the third operation stream; and a polynomial generator that decodes the encoded data using the fourth operation stream.

The data decoding apparatus includes a communication unit receiving a bit signal with encoded data; a first operation unit performing a bit shift on the bit signal by a first length corresponding to a length of a spreading code used to encode the data to generate a first operation stream; a second operation unit generating a second operation stream from which the spreading code is removed using the bit signal and the first operation stream; a third operation unit performing a bit shift on the second operation stream by a second length to generate a third operation stream; a fourth operation unit generating a fourth operation stream from which the data is removed using the second operation stream and the third operation stream; and a polynomial generator generating a generator polynomial capable of decoding the data encoded using the fourth operation stream.

An error correction circuit includes a control unit suitable for receiving a data chunk including a plurality of data blocks, each of the data blocks being included in a corresponding codeword of a first direction and a corresponding codeword of a second direction; and a decoder suitable for performing a decoding operation on a codeword, which is selected by the control unit, in the data chunk, wherein the control unit calculates a first reference value by applying a correction capability value of the first direction to a flag of the first direction, calculates a second reference value by applying a correction capability value of the second direction to a flag of the second direction, selects a priority direction from the first direction and the second direction based on the first reference value and the second reference value, and preferentially selects codewords of the priority direction for decoding operations.