Embodiments provide a transfer method for wirelessly transferring data in a communication system (e.g. a sensor network or telemetry system). The data includes core data and extension data, wherein the core data is encoded and distributed in an interleaved manner to a plurality of core sub-data packets, wherein the extension data is encoded and distributed in an interleaved manner to a plurality of extension sub-data packets, wherein at least a part of the core data contained in the core sub-data packets is needed for receiving the extension data or extension data packets.

The invention relates to the transmission and reception of non-binary error correcting code words. The transmission method includes a first modulation (56) which implements a set of q sequences comprising q-1 sequences of q-1 chips, each sequence being obtained by circular shifting of a basic pseudo-random sequence, and a partially invariant sequence, invariant to a predetermined subset of circular shifts. The first modulation (56) further implements an association between each code word symbol and a sequence of the set of sequences wherein said finite field GF.sub.q has a non-zero primitive element, the symbol zero being associated with said partially invariant sequence and a symbol equal to a power j of the primitive element, j being an integer comprised between 0 and q-2, being associated with a pseudo-random sequence determined by j circular shifts of the basic pseudo-random sequence.

The present invention is directed to communication systems and methods. In a specific embodiment, the present invention provides a receiver that includes an error correction module. A syndrome value, calculated based on received signals, may be used to enable the error correction module. The error correction module includes an error generator, a Nyquist error estimator, and a decoder. The decoder uses error estimation generated by the Nyquist error estimator to correct the decoded data. There are other embodiments as well.

Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.

Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.

Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.

Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.

method and apparatus for synchronizing replicated data in a storage network. In an embodiment, a method begins by a processing module of a computing device identifying a first storage set and a second storage set for replicated storage of a data object. The processing module initiates storage of the data object in both the first and second storage sets, and further maintains a synchronization status for the data object. The processing module determines, based at least in part on the synchronization status, to resynchronize the first storage set and the second storage set. In response to determining to resynchronize the first storage set and the second storage set, the processing module identifies a latest available revision of the data object, determines that the second storage set requires the latest available revision of the data object to maintain synchronization, and facilitates storage of the identified latest available revision of the data object in the second storage set.

An encoding circuit includes an allocator configured to allocate symbols among a plurality of symbols within a constellation of multilevel modulation and correspond to values of a plurality of bit stings, a converter configured to convert values of each of bit strings excluding a first bit string so that, as a region within the constellation is closer to the center of the constellation, the number of symbols allocated in the region is larger, a switch configured to switch between a first time period in which a first error correction code is inserted and a second time period in which the first error correction code is not inserted, and an insertor configured to generate the first error correction code from a second bit string in the second time period and inserts the first error correction code in two or more bit strings in the first time period according to the switching.

Transmitter for chirp-modulated radio signals comprising a chirp generator configured to generate a series of chirp signals, wherein each chirp carries an element of information encoded as a cyclic shift, and has a phase encoding an error correction code dependent form the cyclic shift of the chirp, the transmitter further comprising a modulator configured to modulate the series of chirp onto a radio signal and a radio transmitter, transmitting the radio signal. receiver for chirp-modulated radio signals, comprising a clock unit and a demodulator configured for demodulating a series of received chirps signal, the demodulator having a dechirp unit, configured for determining a cyclic shift of each received chirp relative to a base chirp and an error correction code based on a phase of the received chirp, the receiver having a synchronism correction unit configured to detect and/or correct an error in the clock unit based on the error correction code.