A method for handling a read error on a block of a memory device is disclosed. In response to a read failure indicating that at least one error handling mechanism has handled the read error on the block and fails to read data stored in the block, a memory test is trigged to be performed on the block. The memory test is configured to determine whether the block malfunctions.

A method for decoding data by an electronic device (100) is provided. The method includes receiving, by the electronic device (100), encoded data. The method includes determining, by the electronic device (100), a sparsity of a plurality of Machine Learning (ML) models (301, 302) of a turbo decoder (150) of the electronic device (100) for decoding the encoded data based on Quality-of-Service (QoS) parameters. The method includes decoding, by the electronic device (100), the encoded data using the turbo decoder (150) based on the determined sparsity.

A memory controller includes, in one embodiment, a memory interface, a plurality of decoders, and a controller circuit. The memory interface is configured to interface with a memory having a plurality of wordlines. Each decoder of the plurality of decoders is configured to determine a bit error rate (BER). The controller circuit configured to generate a plurality of bit-error-rate estimation scan (BES) hypotheses for one wordline of the plurality of wordlines, divide the plurality of BES hypotheses among the plurality of decoders, receive BER results from the plurality of decoders based on the plurality of BES hypotheses, and adjust one or more read locations of the one wordline based on the BER results from the plurality of decoders.

A transmission processing method includes: performing encoding or decoding, or instructing a second communication device to perform encoding or decoding. The encoding or decoding uses a multi-level structure.

A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

Methods, systems, and devices for error correction for internal read operations are described. In some memory systems, a memory device may perform an internal read operation, in which the memory device reads data internal to the memory device (e.g., without sending the data to a memory system controller). To detect and correct errors during an internal read operation, the memory device may use an error control circuit on a memory die. The error control circuit on the memory die may operate on the same codeword, including the same data and same parity bits, as an error control circuit at the memory system controller, effectively reusing the stored parity bits for host read operations and internal read operations. To reduce the decoding overhead at the memory device, the error control circuit on the memory die may support detecting fewer errors than the error control circuit at the memory system controller.

A memory system includes an encoder and a decoder. The encoder is configured to generate multi-dimensionally-coded data to be written into the non-volatile memory. Data bits of the multi-dimensionally-coded data are grouped into first and second dimensional codes with respect to first and second dimensions, respectively. The decoder is configured to, with respect to each of the first and second dimensional codes included in read multi-dimensionally-coded data, generate a syndrome value of the dimensional code, generate low-reliability location information, generate a soft-input value based on the syndrome value and the low-reliability location information, decode the dimensional code through correction of the dimensional code using the soft-input value, and store modification information indicating a bit of the dimensional code corrected through the correction and reliability information indicating reliability of the correction. The decoder generates the soft-input value also based on the modification information and the reliability information in the memory.

A storage device includes: a memory; and a processor configured to, at the time of writing data into the memory, generate a first check code common to a plurality of types of error correction codes from the data on the basis of a correlation relationship between the plurality of types of error correction codes, add the first check code to the data and write the data into the memory, convert the first check code into a second check code based on any one of the plurality of types of error correction codes at the time of reading the data from the memory, and perform error correction by using the second check code.

A processing device in a memory system receives a request to read data from a memory device. In response to receiving the request, the processing device performs an iterative error correction process on the data, wherein at least one iteration after a first iteration in the error correction process uses a criterion that is based at least partially on a previous iteration or partial iteration, and wherein performing the iterative error correction process comprises flipping any bits in the data having an associated number of unsatisfied parity check equations that satisfies a threshold criterion associated with the previous iteration.

A method of responding to a read request from a host includes: obtaining read data from a memory device, performing first iteration ECC decoding on the read data to generate a plurality of pieces of decoded data, selecting one of the plurality of pieces of decoded data as intermediate data as intermediate data, generating preprocessed data based on the read data and the intermediate data and performing second iteration ECC decoding on the preprocessed data when the first iteration ECC decoding fails, and outputting the intermediate data to the host when the first iteration ECC decoding succeeds.