An apparatus and method for multiplexing signals using layered division multiplexing are disclosed. A signal multiplexing apparatus according to an embodiment of the present invention includes a combiner configured to combine a core layer signal and an enhanced layer signal at different power levels, and a time interleaver configured to perform interleaving applied to both the core layer signal and the enhanced layer signal.

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

A receiver is provided. The receiver includes: a first decoder configured to decode a superposition-coded signal by using a parity check matrix to generate Low Density Parity Check (LDPC) information word bits and first parity bits corresponding to a first layer signal; an encoder configured to encode the LDPC information word bits and the first parity bits to generate second parity bits, or encode the LDPC information word bits to generate the first parity bits and the second parity bits, by using the parity check matrix; and a second decoder configured to decode a signal which is generated by removing the first layer signal, corresponding to the LDPC information word bits, the first parity bits, and the second parity bits, from the superposition-coded signal, to reconstruct bits transmitted through the second layer signal.

The disclosure proposes a technique for achieving validity decision performance of a suitable level in communication and broadcasting systems using a polar code. The polar code is a channel code in which it is difficult to use a syndrome check due to a successive cancellation (SC)-based decoding operation and coding structure. Accordingly, in the communication of the related art and broadcasting systems using the polar code, a validity check of a decoding result has been performed by using a path-metric (PM) generated during decoding and a concatenated error detection code, such as a cyclic redundancy check (CRC) code. However, it is difficult to achieve target error detection performance only via such methods when the length of the CRC code is short or when input and output lengths of a code are short. In this regard, an embodiment of the disclosure proposes a method for obtaining a Euclidean distance-based metric between a received signal and a decoded signal by using an estimated codeword output bit sequence, and performing post error detection based on this.

Disclosed are devices, systems and methods for error correction encoding and decoding. A memory controller includes an error correction encoder for generating a codeword by performing error correction encoding, using a parity check matrix including a plurality of sub-matrices; and an error correction decoder for performing error correction decoding on a read vector corresponding to the codeword on a column layer basis while sequentially selecting column layers of the parity check matrix used for the error correction encoding, in the error correction decoding, the column layer including a set of columns of the parity check matrix. Rows included in the parity check matrix are grouped into a plurality of row groups, and at most one cyclic permutation matrix (CPM) is included for each column layer in each of the row groups.

An encoder receives a concatenated encoder input block d, splits d into an outer code input array a, and encodes a using outer codes to generate an outer code output array b. The encoder generates, from b, a concatenated code output array x using a layered polarization adjusted convolutional (LPAC) code. A decoder counts layers and carries out an inner decoding operation for a layered polarization adjusted convolutional (LPAC) code to generate an inner decoder decision {tilde over (b)}.sub.i from a concatenated decoder input array y and a cumulative decision feedback ({circumflex over (b)}.sub.1, {circumflex over (b)}.sub.2, . . . , {circumflex over (b)}.sub.i−1). The decoder carries out an outer decoding operation to generate from {tilde over (b)}.sub.i an outer decoder decision â.sub.i, and carries out a reencoding operation to generate a decision feedback {circumflex over (b)}.sub.i from â.sub.i, where the number of layers is an integer greater than one, with a concatenated decoder output block {circumflex over (d)} being generated from outer decoder decisions.

A receiver is provided. The receiver includes: a first decoder configured to decode a superposition-coded signal by using a parity check matrix to generate Low Density Parity Check (LDPC) information word bits and first parity bits corresponding to a first layer signal; an encoder configured to encode the LDPC information word bits and the first parity bits to generate second parity bits, or encode the LDPC information word bits to generate the first parity bits and the second parity bits, by using the parity check matrix; and a second decoder configured to decode a signal which is generated by removing the first layer signal, corresponding to the LDPC information word bits, the first parity bits, and the second parity bits, from the superposition-coded signal, to reconstruct bits transmitted through the second layer signal.

The system and method described provide correction of modulation symbol errors which may occur during audio pairing of computing devices. The transmission between the computing devices comprises a six modulation symbol (24 bit) token containing transaction information and a two check symbol (8 bit) cyclic redundancy check (“CRC”). Error probabilities of symbols are be used to identify probable symbol error locations and the number of errors contained in the received transmission during the symbol decoding process. If there is a single modulation symbol error, the 16 possible combinations of bit values are cycled through until one combination passes the CRC check. If there are two modulation symbol errors, the 256 possible combinations of bit values are cycled through until two combinations pass the CRC check.

An apparatus and method for multiplexing signals using layered division multiplexing are disclosed. A signal multiplexing apparatus according to an embodiment of the present invention includes a combiner configured to combine a core layer signal and an enhanced layer signal at different power levels, and a time interleaver configured to perform interleaving applied to both the core layer signal and the enhanced layer signal.

According to certain embodiments, a method is provided for generating soft information for code bits of polar codes. The method includes receiving, by a decoder of a receiver, soft information associated with coded bits from a first module of the receiver and using a tree structure of the polar code to generate updated soft information. The updated soft information is output by the decoder for use by a second module of the receiver.