There are provided methods and systems for on-ASIC error control coding for verifying the integrity of data from a memory. For example, there is provided a method for encoding data into a beat. The method can be executed by a digital system configured to receive the data and construct the beat. The method includes assembling, by the digital system, a plurality of words consecutively. The plurality of words can include a first set of words in which each word has a length W, where W is the beat width. The plurality of words can further include a second set of words in which each word has a length that is smaller or equal to W. The method can further include constructing a parity word of length W, wherein each bit in the parity word is a parity associated with a distinct word in the first and second set of words. The method further includes adding the parity word to the plurality of words to form the beat.

A method and a decoder for receiving a message encoded in Turbo Codes and modulated for transmission as an analog signal includes: (a) demodulating the analog signal to recover the Turbo Codes; and (b) decoding the Turbo Codes to recover the message using an iterative Turbo Code decoder, wherein the decoding includes performing an error detection after a predetermined number of iterations of the Turbo Code decoder to determine whether or not an error has occurred during the transmission. The predetermined number of iterations may be, for example, two. Depending on the result of the error detection, the decoding may stop, a request for retransmission of the message may be sent, or further iterations of decoding in the Turbo Code decoder may be carried out.

The present disclosure relates to a decoding method. The decoding method includes a sequentially determining series of source bits from a codeword by performing a first decoding operation and a second decoding operation. For instance, a series of N source bits may be divided into a first bit group of X source bits and a second bit group of Y source bits. The initial X source bits are sequentially determined in the first decoding operation and the remaining Y source bits are sequentially determined in the second decoding operation. The first decoding operation includes sorting at least 2L reliability values, which are calculated from L bit sequences, where L is an integer greater than 0. The second decoding operation includes determining a source bit in each of the L bit sequences, based on the at least 2L reliability values.

An apparatus is described. The apparatus includes a memory chip. The memory chip has an error correction code (ECC) encoder logic circuit and an ECC decoder logic circuit. The ECC decoder logic circuit is to place an additional one or more errors that result from incorrect error correction applied to a read code word into a same block of multiple blocks of the read code word's raw data bit portion where original errors in the read code word existed before the read code word was decoded by the ECC decoder logic circuit.

A cyclic redundancy check, CRC, decoder circuit having a K-bit input bit sequence, s, comprising information bits and CRC bits; and at least one processor (P) configured to perform a CRC decode computation and configured to: use an inverse of a predefined CRC generator polynomial that encoded the K-bit input bit sequence, s, to produce a data set; compute a CRC syndrome from the data set; and determine whether the CRC syndrome contains any one-valued bits indicative of a CRC error. An LUT stores one or more rows of a CRC generator matrix (G) generated from the inverse of the predefined CRC generator polynomial. A set of mod(−K,P) zero-valued filler bits are appended to an end of the K-bit input bit sequence, wherein an order of the rows in the CRC generator matrix (G) is reversed and aligned with the input bits of the input stream.

An apparatus is described. The apparatus includes a memory chip. The memory chip has an error correction code (ECC) encoder logic circuit and an ECC decoder logic circuit. The ECC decoder logic circuit is to place an additional one or more errors that result from incorrect error correction applied to a read code word into a same block of multiple blocks of the read code word's raw data bit portion where original errors in the read code word existed before the read code word was decoded by the ECC decoder logic circuit.

A cyclic redundancy check, CRC, decoder circuit having a K-bit input bit sequence, s, comprising information bits and CRC bits; and at least one processor (P) configured to perform a CRC decode computation and configured to: use an inverse of a predefined CRC generator polynomial that encoded the K-bit input bit sequence, s, to produce a data set; compute a CRC syndrome from the data set; and determine whether the CRC syndrome contains any one-valued bits indicative of a CRC error. An LUT stores one or more rows of a CRC generator matrix (G) generated from the inverse of the predefined CRC generator polynomial. A set of mod(−K,P) zero-valued filler bits are appended to an end of the K-bit input bit sequence, wherein an order of the rows in the CRC generator matrix (G) is reversed and aligned with the input bits of the input stream.

The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.

A device includes a controller, and the controller includes a root detection circuit having multiple sets of multipliers. A method includes configuring the root detection circuit according to a degree of a polynomial. In response to detection of a root of multiple roots of the polynomial, a configuration of the root detection circuit is modified based on a polynomial degree reduction (PDR) scheme. Depending on the particular implementation, the device may be implemented in a data storage device, a communication system (e.g., a wireless communication device or a wired communication device), or another electronic device.

The disclosure relates to a method performed in a cyclic redundancy check, CRC, device for calculating, based on a generator polynomial G(x), a CRC code for a message block. The method comprises receiving n segments of the message block in forward order or in reverse order, wherein at least one segment is received in reverse order; calculating for each of the n segments a respective segment CRC code based on the generator polynomial G(x), wherein each segment CRC is calculated according to the received order of the segment; aligning each of the n segment CRC codes; and calculating the CRC code for the message block by adding together each of the aligned n segment CRC codes. The disclosure also relates to a device, computer program and computer program product.