A decoding method, a memory storage device, and a memory control circuit unit are provided. The decoding method includes: reading a codeword from a memory module and estimating error level information of the codeword; inputting the codeword and the error level information to an error checking and correcting circuit through a first message channel and a second message channel respectively; determining whether the error level information meets a default condition; if yes, inputting the codeword to a first decoding engine of the error checking and correcting circuit for decoding; otherwise, inputting the codeword to a second decoding engine of the error checking and correcting circuit for decoding, wherein a power consumption of the first decoding engine is lower than that of the second decoding engine, and a decoding success rate of the first decoding engine is lower than that of the second decoding engine. Therefore, an operating flexibility for decoding may be improved.

A low-density parity-check (LDPC) decoder comprising a pre-processor, a core decoder, and a post-processor. The pre-processor is configured to transform a received log-likelihood-ratio (LLR) sequence into a form that enables the core decoder to toggle at a reduced rate during iterative decoding processing thereof. Upon stoppage of the decoding processing corresponding to the LLR sequence, the post-processor operates to apply a complementary transformation to the output of the core decoder, which recovers the corresponding codeword of the LDPC code. An example embodiment of the LDPC decoder operating in this manner may be able to beneficially reduce the power consumption therein by about 10%.

A data encoding device suitable for encoding a plurality of LDPC codes is disclosed including an input interface and an output interface, and a first circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of a first multiplexer circuit, a second circuit for encoding quasi-cyclic LDPC code, connected at an input to the input interface and at an output to the input of the first multiplexer circuit, a third circuit for encoding quasi-cyclic LDPC code, connected at an input to the output of the first multiplexer circuit and at an output to the input of a second multiplexer circuit.

Systems, methods, and instrumentalities are described herein that may be used for reduced complexity polar encoding and decoding. There may be a set of encoding nodes to be used for polar encoding. An encoding node may be associated with a bit index and/or a relaxation level. A relaxation attribute may be selected for the encoding node. A relaxation group may be determined based on the relaxation attributes. The relaxation group may include two encoding nodes associated with consecutive bit indexes, an initial relaxation level, and the first relaxation attribute. A final relaxation level may be determined. Relaxation may be performed on the encoding nodes in the relaxation group. For example, an XOR operation between the encoding nodes may be omitted. Relaxation may be performed on the encoding nodes associated with each relaxation level up to the final relaxation level.

A decoding system, a decoding controller, and a decoding control method are provided. In the decoding system, a decoding controller is disposed between two adjacent decoders. The decoding controller determines whether to perform turn-off based on a non-turn-off indication received by a previous-stage decoder, a turn-off indication output by the previous-stage decoder, and historical turn-off probability statistics. This is equivalent to adding a buffer zone between the two adjacent decoders.

An encoding circuit includes: a polar encoding unit capable of encoding a polar code of N bits; a frozen bit adding unit that generates a first sequence by adding frozen bits to an input signal; and a bit arrangement changing unit that: generates a second sequence of N bits by arranging the first sequence in the second sequence according to an arrangement rule dependent on a ratio of N.sub.t bits, being a code length of a polar code to be encoded and being N bits or less, and N bits, and setting bit values at bit positions other than positions where the first sequence is arranged in the second sequence to zero when N.sub.t bits are less than N bits; and inputs the second sequence to the polar encoding unit. A code word of N.sub.t bits is generated by thinning processing based on a result of encoding the second sequence.

The disclosure relates to a method performed by an apparatus for decoding an encoded signal in a communication system according to an embodiment of the disclosure may include an operation of receiving an encoded signal including a plurality of codeword bits, an operation of determining a first log-likelihood ratio (LLR) for the plurality of codeword bits, and an operation of performing iterative decoding a predetermined number of times based the first LLR, and the plurality of codeword bits may include a codeword bit included in a first subset and a codeword bit included in a second subset, and the operation of performing iterative decoding may include determining a second LLR only for the codeword bit included in the first subset of the plurality of codeword bits, and estimating, based on the second LLR, a bit value only for the codeword bit included in the first subset.

A processing circuit configured to: receive original data; partition the original data into a plurality of original q-bit words; assemble a data packet including N original q-bit words from the plurality of original q-bit words; identify a first encoder value and a second encoder value that are absent from the values of the N original q-bit words; encode the N original q-bit words based on a one-to-one mapping from q-bit original values to q-bit encoded values based on the first encoder value and the second encoder value to generate N encoded q-bit payload words, the N encoded q-bit payload words being free of words that are all-zeroes and free of words that are all-ones; generate a key representing the first encoder value and the second encoder value; and transmit the key and the N encoded q-bit payload words.

Provided are an apparatus and method for parallel Reed-Solomon (RS) encoding. A parallel RS encoding apparatus includes a coefficient generator configured to calculate a parity symbol matrix and group coefficients of each row or each column of the parity symbol matrix to correspond to the number of parallel paths, a data delayer configured to delay a parallel input information symbol block including symbols of the number of parallel paths so that calculation of a parity symbol is processed in order, a parity symbol calculator configured to calculate, based on the grouped coefficients outputted from the coefficient generator and the parallel input information symbol block delayed by the data delayer, the parity symbol, and a parallel outputter configured to output a codeword generated based on the parity symbol outputted from the parity symbol calculator and the parallel input information symbol block delayed by the data delayer.

The present disclosure relates to a 5.sup.th generation (5G) or pre-5G communication system for supporting a data transmission rate higher than that of a post-4.sup.th generation (4G) communication system such as Long Term Evolution (LTE). The present disclosure is for decoding a polar code in a communication system. An operation method of a reception device comprises the steps of: receiving data encoded by means of a polar code and comprising a plurality of bits; confirming one or more bits which do not require a decoding operation among the plurality of bits; and decoding at least some of the bits remaining after excluding the one or more bits.