A wireless receiving device comprises a low-density parity check (LDPC) decoding circuit, comprising a circular shifter constructed and arranged to simultaneously process multiple code words of a parity check matrix configured for different wireless communication standards, including performing a cyclic shift operation of the multiple code words to align with one or more requisite check nodes of a decoder and a logic circuit at an output of the circular shifter constructed and arranged for a matrix larger than the parity check matrix and that includes components having excess hardware due to the construction and arrangement for the larger matrix to decode the multiple code words of the smaller parity check matrix for output to the one or more requisite check nodes.

An error rate measuring apparatus includes: an operation unit that sets a codeword length, an FEC symbol length, and an FEC symbol error threshold; error counting means for counting FEC symbol error and an uncorrectable codeword; a display unit that performs display by setting one zone of a display area as one FEC symbol length, matching a zone length of a horizontal axis of the display area with one codeword length, and performing line feed in codeword length units according to presence or absence of the FEC symbol error in FEC symbol length units based on a counting result; search means for searching for the uncorrectable codeword starting from the cursor on the identification display; and display control means for performing display control of the cursor at a position of a head error of the searched uncorrectable codeword.

A circuit with an interface, a transmit data register coupled to the interface, a storage device coupled to the transmit data register and including a plurality of storage locations, each storage location adapted to store a data unit, and a serial register coupled between the storage device and an output. The circuit also includes a CRC generation circuit having an input coupled between an output of the transmit data register and the storage device. The CRC generation circuit includes a first CRC generation block for providing a CRC in response to an X-bit data unit and an X-bit polynomial and a second CRC generation block with a collective X-bit input for providing a CRC in response to an X-bit data unit and a 2X-bit polynomial in a single clock cycle and a 2X-bit data unit and a 2X-bit polynomial in two clock cycles.

An error rate measuring apparatus includes: an operation unit that sets a codeword length, an FEC symbol length, and an FEC symbol error threshold in accordance with a communication standard of a device under test W; error counting means for counting FEC symbol error detected at one FEC symbol interval and an uncorrectable codeword; a display unit that identifies and displays bit string data according to presence or absence of the FEC symbol error in FEC symbol length units based on a counting result; and display control means for performing display control by setting one zone of a display area of identification display as one FEC symbol length, matching a zone length of a horizontal axis of the display area with one codeword length, and performing line feed in codeword length units.

An error rate measuring apparatus includes: an operation unit that sets a codeword length, an FEC symbol length, and an FEC symbol error threshold in accordance with a communication standard of a device under test W; error counting means for counting FEC symbol error detected at one FEC symbol interval and an uncorrectable codeword; a display unit that identifies and displays bit string data according to presence or absence of the FEC symbol error in FEC symbol length units based on a counting result; and display control means for performing display control by setting one zone of a display area of identification display as one FEC symbol length, matching a zone length of a horizontal axis of the display area with one codeword length, and performing line feed in codeword length units.

An error rate measuring apparatus includes: an operation unit that sets a codeword length, an FEC symbol length, and an FEC symbol error threshold; error counting unit for counting FEC symbol error and an uncorrectable codeword; a display unit that performs display by setting one zone of a display area as one FEC symbol length, matching a zone length of a horizontal axis of the display area with one codeword length, and performing line feed in codeword length units according to presence or absence of the FEC symbol error in FEC symbol length units based on a counting result; search unit for searching for the uncorrectable codeword starting from the cursor on the identification display; and display control unit for performing display control of the cursor at a position of a head error of the searched uncorrectable codeword.

A Bluetooth data packet processing method is disclosed. According to the Bluetooth data packet processing method, a standard Bluetooth baseband protocol is extended, so that a Bluetooth node can also support polar encoding/decoding based on compatibility with the standard Bluetooth protocol. When processing a Bluetooth data packet, the Bluetooth node may choose to perform polar encoding on the data packet by using an extended Bluetooth baseband protocol, to improve demodulation performance of a Bluetooth receiver, and improve an anti-interference capability of a Bluetooth system.

A detection circuit performs a turbo detection process to recover a frame of data symbols from a received signal, the data symbols of the frame having been effected, during transmission, by a Markov process with the effect that the data symbols of the frame in the received signal are dependent one or more preceding data symbols which can be represented as a trellis having a plurality of trellis stages. The detection circuit comprises a plurality of processing elements, each of the processing elements is associated with one of the trellis stages representing the dependency of the data symbols of the frame according to the Markov process and each of the processing elements is configured to receive one or more soft decision values corresponding to one or more data symbols associated with the trellis stage, and each of one or more of the processing elements is configured, in one clock cycle to receive fixed point data representing a priori forward state metrics a priori backward state metrics, and fixed point data representing a priori soft decision values for the one or more data symbols being detected for the trellis stage. For each of a plurality of clock cycles of the turbo detection process, the detection circuit is configured to process, for each of the processing elements representing the trellis stages, the a priori information for the one or more data symbols being detected for the trellis stage associated with the processing element, and to provide the extrinsic soft decision values corresponding to the one or more data symbols for a next clock cycle of the turbo detection process.

The present invention discloses a method for fusing baseband resources between networks of different standards. The method includes the following steps: performing coding on baseband data by using a coding scheme of a first network, and then performing modulation by using a modulation scheme of a second network. The present invention further discloses a corresponding base station and a terminal. In the present invention, in a case of collocation/co-device or a co-baseband resource pool, a correspondence between channel coding/de-coding and modulation/demodulation in each network is changed to enable the network to implement dynamic matching according to a specific factor such as a network status service type, thereby improving system performance of the network and significantly improving transmission performance.

A wireless receiving device comprises a low-density parity check (LDPC) decoding circuit, comprising a circular shifter constructed and arranged to simultaneously process multiple code words of a parity check matrix configured for different wireless communication standards, including performing a cyclic shift operation of the multiple code words to align with one or more requisite check nodes of a decoder and a logic circuit at an output of the circular shifter constructed and arranged for a matrix larger than the parity check matrix and that includes components having excess hardware due to the construction and arrangement for the larger matrix to decode the multiple code words of the smaller parity check matrix for output to the one or more requisite check nodes.