Patent classifications
H03M13/6522
LOW-LATENCY SEGMENTED QUASI-CYCLIC LOW-DENSITY PARITY-CHECK (QC-LDPC) DECODER
Systems and methods which provide parallel processing of multiple message bundles for a codeword undergoing a decoding process are described. Embodiments provide low-latency segmented quasi-cyclic low-density parity-check (QC-LDPC) decoder configurations in which decoding process tasks are allocated to different segments of the low-latency segmented QC-LDPC decoder for processing multiple bundles of messages in parallel. A segmented shifter of a low-latency segmented QC-LDPC decoder implementation may be configured to process multiple bundles of a plurality of edge paths in parallel. Multiple bundles of messages of a same check node cluster (CNC) are processed in parallel. Additionally, multiple bundles of messages of a plurality of CNCs are processed in parallel.
Low-latency segmented quasi-cyclic low-density parity-check (QC-LDPC) decoder
Systems and methods which provide parallel processing of multiple message bundles for a codeword undergoing a decoding process are described. Embodiments provide low-latency segmented quasi-cyclic low-density parity-check (QC-LDDC) decoder configurations in which decoding process tasks are allocated to different segments of the low-latency segmented QC-LDPC decoder for processing multiple bundles of messages in parallel. A segmented shifter of a low-latency segmented QC-LDPC decoder implementation may be configured to process multiple bundles of a plurality of edge paths in parallel. Multiple bundles of messages of a same check node cluster (CNC) are processed in parallel. Additionally, multiple bundles of messages of a plurality of CNCs are processed in parallel.
ENCODING AND DECODING OF CONTROL SIGNALING WITH SECTIONAL REDUNDANCY CHECK
Certain aspects of the present disclosure relate to techniques and apparatus for increasing decoding performance and/or reducing decoding complexity. An exemplary method generally includes obtaining a payload to be transmitted, partitioning the payload into a plurality of payload sections, deriving redundancy check information for each respective payload section of the plurality of payload sections, merging the redundancy check information for each payload section with the plurality of payload sections to form a sequence of bits, and generating a codeword by encoding the sequence of bits using an encoder. Other aspects, embodiments, and features are also claimed and described.
INTERLEAVING AND MAPPING METHOD AND DEINTERLEAVING AND DEMAPPING METHOD FOR LDPC CODEWORD
An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises: performing first bit interleaving on a check part of the LDPC codeword to obtain a check bit stream; splicing an information bit part of the codeword and the check bit stream into a codeword after the first bit interleaving; dividing the codeword after the first bit interleaving into multiple consecutive bit subblocks in a predetermined length, and changing the order of the bit subblocks according to a corresponding permutation order (bit-swapping pattern) to form a codeword after second bit interleaving; dividing the codeword after the second bit interleaving into two parts, and writing the two parts into storage space in a column order respectively and reading the two parts from the storage space in a row order respectively to obtain a codeword after third bit interleaving; and performing constellation mapping on the codeword after the third bit interleaving according to a constellation diagram to obtain a symbol stream; the permutation orders (bit-swapping patterns) and the constellation diagrams used in the interleaving and mapping processing of LDPC codes with different code rates, code length and LDPC code tables are designed and optimized using theoretical analysis. The technical solution reduces the receiving threshold of the receiving end.
System and method for processing control information
A system and method for allocating network resources are disclosed herein. In one embodiment, the system and method are configured to perform: determining a redundancy version and a new data indicator indicated by control information; determining a base graph of a low density parity check code based on which of a plurality of predefined conditions the redundancy version, and/or the new data indicator satisfy; and sending a signal comprising information bits that are encoded based on the determined base graph of the low density parity check code.
LOW COMPLEXITY DECODER AND DECODING METHOD BASED ON CODE OF BIT NODE
Provided is a decoder that is at least temporarily implemented by a processor of a computing device. The decoder includes a calculator configured to repeatedly perform a calculation of a bit node and a calculation of a check node for an input frame, a processor configured to determine whether to input the bit node to a next calculation of the check node based on a code of the bit node, and an outputter configured to output a decoded code based on the bit node determined to be input.
Rate matching performing method for LDPC code and communication device therefor
A method by which a terminal performs rate matching for a low density parity check (LDPC) code can comprise the steps of: determining any one transport block size (TBS) among a plurality of TBSs set for rate matching in the terminal; and performing rate matching for the LDPC code on the basis of the selected TBS. The UE is capable of communicating with at least one of another UE, a UE related to an autonomous driving vehicle, a base station or a network.
METHOD AND APPARATUS FOR LOW-DENSITY PARITY-CHECK (LDPC) CODING
An apparatus and method are described. The apparatus includes a transceiver and processor, which attach transport block (TB) level CRC bits to a TB, select an LDPC base graph (BG) based on a code rate (CR) and TB size of the TB including TB level CRC bits, determine a number of code blocks (CBs) to use for segmenting the TB including TB level CRC bits depending on the selected LDPC BG, determine a single CB size for each of the CBs based on the number of CBs, segment the TB including TB level CRC bits into the CBs based on the number of CBs and CB size, pad zeros to a last CB of the CBs in the segmented TB, attach CB level CRC bits to each CB in the segmented TB, encode each CB in the segmented TB using the selected LDPC base graph, and transmit the encoded CBs.
System and method for processing control information
A system and method for allocating network resources are disclosed herein. In one embodiment, the system and method are configured to perform: determining a redundancy version and a new data indicator indicated by control information; determining a base graph of a low density parity check code based on which of a plurality of predefined conditions the redundancy version, and/or the new data indicator satisfy; and sending a signal comprising information bits that are encoded based on the determined base graph of the low density parity check code.
SYSTEM AND METHOD FOR PROCESSING CONTROL INFORMATION
A system and method for allocating network resources are disclosed herein. In one embodiment, the system and method are configured to perform: determining a redundancy version and a new data indicator indicated by control information; determining a base graph of a low density parity check code based on which of a plurality of predefined conditions the redundancy version, and/or the new data indicator satisfy; and sending a signal comprising information bits that are encoded based on the determined base graph of the low density parity check code.