Embodiments of the present disclosure relate to a binary clustered forward error correction encoding scheme. Systems and methods are disclosed that define binary clustered encodings of the media packets from which forward error correction (FEC) packets are computed. The different encodings specify which media packets in a frame are used to compute each FEC packet (a frame includes M media packets). The different encodings may be defined based on the quantity of media packets in a frame, M≤floor(2.sup.N), where each bit of the binary representation of N is associated with a different cluster pair encoding of the media packets. Each cluster pair includes a cluster for which the bit=0 and a cluster for which the bit=1. Computing FEC packets using at least two cluster pair encodings provides redundancy for each media packet, thereby improving media packet recovery rates.

A decoding method and device are provided. The method includes: decoding grouped original data in parallel by a first decoding unit to obtain grouped decoded data; decoding merged grouped decoded data by a second decoding unit to obtain decoded data; and if the sum of the lengths of the decoded data is an integer multiple of an upper limit of the decoding times of the second decoding unit, updating the first decoding unit and the second decoding unit, and if the sum of the lengths of the decoded data is not an integer multiple of the upper limit of the decoding times of the second decoding unit, updating the second decoding unit to obtain the decoded data again, until the sum of the lengths of the decoded data is equal to a decoding length, and merging the decoded data to serve as a decoding result of the original data.

Systems and methods are provided for decoding data read from non-volatile storage devices. A method that may include decoding a first codeword read from a storage location of a non-volatile storage device using a first decoder without soft information, determining that the first decoder has failed to decode the first codeword, decoding the first codeword using a second decoder without soft information, determining that the second decoder has succeeded in decoding the first codeword, generating soft information associated with the storage location using decoding information generated by the second decoder and decoding a subsequent codeword from the storage location using the soft information associated with the storage location. The second decoder may be more powerful than the first decoder.

The invention refers to the parallel calculation method for polarization coding (PCPE) for channel coding technique in 5th next generation mobile communication systems which includes to split N-bits input sequence into X parallel streams, each stream has Y bits; to multiply Y bits at each stream by the columns of the Kronecker matrix G.sub.Y, the results are displayed in rows according to the principle of bit elimination; and to multiply the matrix obtained with the columns of the Kronecker matrix G.sub.X according to the sample repeat and scalar multiplication. In addition, the invention also refers to the polarization coding system according to the Parallel Computation for Polarization Encoding (PCPE) for the channel coding technique in the 5th next generation mobile communication system.

Systems and methods which provide parallel processing of multiple message bundles for a codeword undergoing a decoding process are described. Embodiments provide low-latency segmented quasi-cyclic low-density parity-check (QC-LDPC) decoder configurations in which decoding process tasks are allocated to different segments of the low-latency segmented QC-LDPC decoder for processing multiple bundles of messages in parallel. A segmented shifter of a low-latency segmented QC-LDPC decoder implementation may be configured to process multiple bundles of a plurality of edge paths in parallel. Multiple bundles of messages of a same check node cluster (CNC) are processed in parallel. Additionally, multiple bundles of messages of a plurality of CNCs are processed in parallel.

The invention relates to an interconnection network for forward error correction encoders and decoders, including N input terminals, N output terminals, and M stages. Each stage includes switching elements having input pins and output pins. The input pins of the switching elements of the first stage are connected to the input terminals, and the output pins of the switching elements of the last stage are connected to the output terminals. The input and output pins of the switching elements of immediately successive stages are connected in a hardwired fashion so as to form a plurality of interconnection sub-networks for routing respective input values from respective output pins of the switching elements of the first stage to respective input pins of the switching elements of the last stage.

Provided are an apparatus and method for parallel Reed-Solomon (RS) encoding. A parallel RS encoding apparatus includes a coefficient generator configured to calculate a parity symbol matrix and group coefficients of each row or each column of the parity symbol matrix to correspond to the number of parallel paths, a data delayer configured to delay a parallel input information symbol block including symbols of the number of parallel paths so that calculation of a parity symbol is processed in order, a parity symbol calculator configured to calculate, based on the grouped coefficients outputted from the coefficient generator and the parallel input information symbol block delayed by the data delayer, the parity symbol, and a parallel outputter configured to output a codeword generated based on the parity symbol outputted from the parity symbol calculator and the parallel input information symbol block delayed by the data delayer.

A memory controller includes, in one embodiment, a memory interface, a plurality of decoders, and a controller circuit. The memory interface is configured to interface with a memory having a plurality of wordlines. Each decoder of the plurality of decoders is configured to determine a bit error rate (BER). The controller circuit configured to generate a plurality of bit-error-rate estimation scan (BES) hypotheses for one wordline of the plurality of wordlines, divide the plurality of BES hypotheses among the plurality of decoders, receive BER results from the plurality of decoders based on the plurality of BES hypotheses, and adjust one or more read locations of the one wordline based on the BER results from the plurality of decoders.

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

A wireless receiving device comprises a low-density parity check (LDPC) decoding circuit, comprising a circular shifter constructed and arranged to simultaneously process multiple code words of a parity check matrix configured for different wireless communication standards, including performing a cyclic shift operation of the multiple code words to align with one or more requisite check nodes of a decoder and a logic circuit at an output of the circular shifter constructed and arranged for a matrix larger than the parity check matrix and that includes components having excess hardware due to the construction and arrangement for the larger matrix to decode the multiple code words of the smaller parity check matrix for output to the one or more requisite check nodes.