The invention relates to an interconnection network for forward error correction encoders and decoders, including N input terminals, N output terminals, and M stages. Each stage includes switching elements having input pins and output pins. The input pins of the switching elements of the first stage are connected to the input terminals, and the output pins of the switching elements of the last stage are connected to the output terminals. The input and output pins of the switching elements of immediately successive stages are connected in a hardwired fashion so as to form a plurality of interconnection sub-networks for routing respective input values from respective output pins of the switching elements of the first stage to respective input pins of the switching elements of the last stage.

An electronic device, configured to perform a series of low-density parity check, LDPC, decoding operations for a parity check matrix, PCM, derived from at least one basegraph having a plurality of rows, includes: two or more check node, CN, sub-processors having input-output (I-O) port(s); and a controller configured to activate a subset of the I-O port(s) based on a current LDPC decoding sub-step of the LDPC decoding operations and the basegraph. The CN sub-processors support: a first single LDPC decoding operation to perform LDPC decoding computations for two or more rows of the PCM that are derived from different orthogonal rows of the plurality of rows in the basegraph; and a second mode whereby two or more of CN sub-processors co-operate to perform LDPC decoding computations for two or more rows of the PCM that are derived from a single row in the basegraph.

A semiconductor system may be provided. The semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to perform an error correction operation. The second semiconductor device may be configured to perform an error correction operation. The semiconductor system may selectively operate the first or second semiconductor devices with regards to error correction operations based on a mode signal.

A read method of a nonvolatile memory device is provided. The method includes storing data sensed from selected memory cells of the nonvolatile memory device into a page buffer, performing an error decoding operation by performing error detection on the sensed data to detect and error, correcting the detected error if the error is detected, and overwriting the page buffer with the corrected data, and de-randomizing data stored in the page buffer by using a seed after the error decoding operation has completed.

Examples of techniques for hardware assisted data protection are disclosed. In one example implementation according to aspects of the present disclosure, a method may include receiving a read data record comprising at least one memory write, the read data record having an associated cyclic redundancy check (CRC). The method may further include calculating, by a hardware module, an expected CRC for the read data record. Additionally, the method may include comparing the expected CRC to a known CRC stored in a known CRC data store. Finally, the method may include authenticating the read data record when the expected CRC matches a corresponding known CRC.

An encoding method, decoding method, encoding device and decoding device for structured LDPC codes. The method includes: determining a basic matrix used for encoding, which includes K0 up-and-down adjacent pairs; and according to the basic matrix and an expansion factor corresponding to the basic matrix, performing an LDPC encoding operation of obtaining a codeword of Nb×z bits according to source data of (Nb−Mb)×z bits, herein z is the expansion factor, and z is a positive integer which is greater than or equal to 1. The provided technical solution is applicable to the encoding and decoding of the structured LDPC, thereby realizing the encoding and decoding of LDPC at the high pipeline speed.

A memory system includes a memory device; and a controller suitable for encoding a message, storing the encoded message in the memory device and decoding the encoded message, wherein the controller is suitable for generating a message matrix including predetermined row codes and predetermined column codes symmetrical to the predetermined row codes, with the message or the encoded message using a block-wise concatenated Bose-Chadhuri-Hocquenghem (BCH) code with a symmetrical structure.

A read method of a nonvolatile memory device is provided. The method includes storing data sensed from selected memory cells of the nonvolatile memory device into a page buffer, performing an error decoding operation by performing error detection on the sensed data to detect and error, correcting the detected error if the error is detected, and overwriting the page buffer with the corrected data, and de-randomizing data stored in the page buffer by using a seed after the error decoding operation has completed.

Methods, systems, and devices for codeword rotation for zone grouping of media codewords are described. A value of a first pointer may be configured to correspond to a first memory address within a region of memory and a value of a second pointer may be configured to correspond to a second memory address within the region of memory. The method may include monitoring access commands for performing access operations within the region of memory, where the plurality of access command may be associated with requested addresses within the region of memory. The method may include updating the value of the second pointer bases on a quantity of the commands that are monitored satisfying a threshold and executing the plurality of commands on locations within the region of memory. The locations may be based on the requested address, the value of the first pointer, and the value of the second pointer.

Example channel circuits, data storage devices, and methods for using an extendable parity code matrix are described. A data unit may be read from a storage medium. Multiple sets of parity bits may be available for the data unit, each set of parity bits having a different number of parity bits corresponding to different parity matrices, including a primary parity matrix and at least one extended parity matrix. The extended parity matrix includes the primary parity matrix and additional rows for increased decoding. Error correction code (ECC) decoding may be selectively performed based on the different sets of parity bits and corresponding parity matrices, resulting in the output of a decoded data unit based on the data unit from the read signal.