Methods, systems, and devices for operating memory cell(s) using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. An output of the error correction circuit may be used to generate syndrome bits, which may be decoded by a syndrome decoder. The syndrome decoder may indicate whether a bit of the data should be corrected by selectively reacting to inputs based on the type of data to be corrected. For example, the syndrome decoder may react to a first set of inputs if the data bit to be corrected is a regular data bit, and react to a second set of inputs if the data bit to be corrected is a redundant data bit.

In encoding systems and methods, data or information is encoded using one or more encoding methodologies to generate encoded data or information corresponding to the data or information. Similarly, in decoding systems and methods, encoded data or information is decoded using one or more decoding methodologies to generate the data or information corresponding to the encoded data or information. The encoding/decoding systems and methods can include polar encoding/decoding systems and methods operable for encoding data or information to generate polar codes and for decoding polar codes to generate the corresponding data or information. The information or data can be control information and application data for communication over networks. The networks can include wireless and wireline networks, and network segments, links or channels, including mixed wireline and wireless networks.

Systems and methods are provided for decoding data read from non-volatile storage devices. A method that may include decoding a first codeword read from a storage location of a non-volatile storage device using a first decoder without soft information, determining that the first decoder has failed to decode the first codeword, decoding the first codeword using a second decoder without soft information, determining that the second decoder has succeeded in decoding the first codeword, generating soft information associated with the storage location using decoding information generated by the second decoder and decoding a subsequent codeword from the storage location using the soft information associated with the storage location. The second decoder may be more powerful than the first decoder.

An encoding circuit includes: a polar encoding unit capable of encoding a polar code of N bits; a frozen bit adding unit that generates a first sequence by adding frozen bits to an input signal; and a bit arrangement changing unit that: generates a second sequence of N bits by arranging the first sequence in the second sequence according to an arrangement rule dependent on a ratio of N.sub.t bits, being a code length of a polar code to be encoded and being N bits or less, and N bits, and setting bit values at bit positions other than positions where the first sequence is arranged in the second sequence to zero when N.sub.t bits are less than N bits; and inputs the second sequence to the polar encoding unit. A code word of N.sub.t bits is generated by thinning processing based on a result of encoding the second sequence.

A device is configured for encoding an input sequence comprising message bits into a codeword using a polar code. The device is configured to sequentially encode each of a plurality of blocks of the input sequence by applying a sliding window to the input sequence, wherein each block of the input sequence is encoded based on an XOR operation of the block and a previous block of the input sequence to obtain a codeword block of the codeword, and sequentially output each obtained codeword block of the codeword.

A system for transmitting information may include a server that generates pseudo-random superpositions, each superposition including multiple packet fragments encoded using a Galois field. The system may transmit the superpositions across a plurality of communication links, which form a single logical path, to a client device. Communication links may include a combination of diverse communication channels, and more preferably one or more low latency (but low bandwidth) communication links and one or more high bandwidth (but high latency) communication links. Advantageously, the use of a plurality of communication links may facilitate transmitting information quickly and reliably.

A quantum computing device is provided, including a logical qubit encoding surface including a plurality of plaquettes. Each plaquette of the plurality of plaquettes may include a plurality of measurement-based qubits. The plurality of measurement-based qubits may include four data qubits and a first ancilla qubit. The first ancilla qubit may be electrically connected to the four data qubits and a second ancilla qubit included in the logical qubit encoding surface.

Systems and methods are provided for decoding data read from non-volatile storage devices. A method that may include decoding a first codeword read from a storage location of a non-volatile storage device using a first decoder without soft information, determining that the first decoder has failed to decode the first codeword, decoding the first codeword using a second decoder without soft information, determining that the second decoder has succeeded in decoding the first codeword, generating soft information associated with the storage location using decoding information generated by the second decoder and decoding a subsequent codeword from the storage location using the soft information associated with the storage location. The second decoder may be more powerful than the first decoder.

An electronic device configured to perform polar coding is described. The electronic device includes a bit pattern generator (3403) configured to successively perform a bit pattern generation process over a series (t=┌n/w┐) of clock cycles; and a counter (c, 4203), operably coupled to the bit pattern generator (3403) and configured to count a number of successive bit pattern generation sub-processes over the series (t=┌n/w┐) of clock cycles. The bit pattern generator (3403) is configured to: provide a successive sub-set of (w) bits from a bit pattern vector (b.sub.k,n) in each successive t=┌n/w┐ clock cycle; where the bit pattern vector comprises n bits, of which ‘k’ bits adopt a first binary value and n−k bits adopt a complementary binary value.

Devices and methods may be used to append a scalable (1) of parity bits in a data packet that scales with a number of data bits in a payload of the data packet. The parity bits may be generated utilizing a table of entries. In some examples, each entry in the table corresponds to a number of the data bits to be included in the payload; and each column of the table may be used to generate a corresponding parity bit of the one or more parity bits.