Patent classifications
H03M13/658
APPARATUS AND METHOD FOR LOW DENSITY PARITY CHECK CODE DECODING
Apparatus and method for low density parity check code decoding in a first processing device, wherein the method includes receiving a first bit-word of a first length related to a log-likelihood ratio of a bit of a signal; obtaining a second bit-word of a second length that is shorter than the first length, wherein obtaining the second bit-word comprises applying a correction to the first bit-word; and determining a message depending on a set of second bit-words, wherein the set of second bit-words includes the second bit-word.
THREE-DIMENSIONAL DATA ENCODING METHOD, THREE-DIMENSIONAL DATA DECODING METHOD, THREE-DIMENSIONAL DATA ENCODING DEVICE, AND THREE-DIMENSIONAL DATA DECODING DEVICE
A three-dimensional data encoding method includes: generating an N-ary tree structure of three-dimensional points included in three-dimensional data, where N is an integer greater than or equal to 2; generating first encoded data by encoding a first branch using a first encoding process, the first branch having, as a root, a first node included in a first layer that is one of layers included in the N-ary tree structure; generating second encoded data by encoding a second branch using a second encoding process different from the first encoding process, the second branch having, as a root, a second node included in the first layer and different from the first node; and generating a bitstream including the first encoded data and the second encoded data.
Processor instructions for iterative decoding operations
A storage circuit is configured to store multiple vectors associated with variable and check nodes of an iterative decoding operation. As part of the iterative decoding operation, a processor circuit is configured to retrieve, from the storage circuit, an intermediate value vector, a first estimation vector, a second estimation vector, and a sign vector, and determine an absolute value of the intermediate value vector. The processor circuit is also configured, using the retrieved vectors, to generate updated values for the first and second estimation vectors as part of determining a bit estimate for a check node included in the iterative decoding operation.
NEURAL SELF-CORRECTED MIN-SUM DECODER AND AN ELECTRONIC DEVICE COMPRISING THE DECODER
An electronic device and an operating method of an electronic device are provided. The operating method includes configuring a self-correction condition for adjusting an information deletion and dropout rate, performing iterative decoding on the received information using decoding factors and a self-correction technique, determining whether decoding of the codeword succeeds or fails, based on a result of the decoding, storing a received signal and the codeword which are successfully decoded, based on a determination result, and optimizing the decoding factors, based on the stored received signal and codeword.
Application of low-density parity-check codes with codeword segmentation
A low-density parity-check (LDPC) decoder performs check node computations as N different segments of the check nodes which have connections only to a codeword segment of length C/N bits as well as check nodes that have connections across the entire codeword of length C. The decoder can include a controller or other compute hardware to decode the codeword, including to perform computations for separate segments of C/N bits of the codeword. The system can perform computations including adjustment of the decode computations based on an expected error rate for selected segments of the codeword.
APPLICATION OF LOW-DENSITY PARITY-CHECK CODES WITH CODEWORD SEGMENTATION
A low-density parity-check (LDPC) decoder performs check node computations as N different segments of the check nodes which have connections only to a codeword segment of length C/N bits as well as check nodes that have connections across the entire codeword of length C. The decoder can include a controller or other compute hardware to decode the codeword, including to perform computations for separate segments of C/N bits of the codeword. The system can perform computations including adjustment of the decode computations based on an expected error rate for selected segments of the codeword.
Non-binary LDPC decoder using binary subgroup processing
In one embodiment, an electronic system includes a decoder configured to decode an encoded data unit using multiple variable nodes and multiple check nodes to perform a low-density parity check (LDPC) decoding process. The encoded data unit can be received from a solid-state memory array. As part of performing the LDPC decoding process, the decoder can (i) convert reliability information representing first non-binary values to reliability information representing first binary values, (ii) determine reliability information representing second binary values using the reliability information representing first binary values, and (iii) convert the reliability information representing the second binary values to reliability information representing second non-binary values.
System and method for processing control information
A system and method for allocating network resources are disclosed herein. In one embodiment, the system and method are configured to perform: determining a redundancy version and a new data indicator indicated by control information; determining a base graph of a low density parity check code based on which of a plurality of predefined conditions the redundancy version, and/or the new data indicator satisfy; and sending a signal comprising information bits that are encoded based on the determined base graph of the low density parity check code.
Low-density parity-check decoding with desaturation
A saturation metric that represents a degree of saturation in a low-density parity-check (LDPC) decoding system that uses a fixed-point number representation is determined. The saturation metric is compared against a saturation threshold. In the event the saturation metric exceeds the saturation threshold, at the end of a decoding iteration, a message is more aggressively attenuated compared to when the saturation metric does not exceed the saturation threshold in order to produce an attenuated message. In the event the saturation metric does not exceed the saturation threshold, at the end of the decoding iteration, the message is less aggressively attenuated compared to when the saturation metric does exceed the saturation threshold in order to produce the attenuated message.
DOUBLE FACTOR CORRECTION TURBO DECODING METHOD BASED ON SIMULATED ANNEALING ALGORITHM
A double factor correction Turbo decoding method based on a simulated annealing algorithm is provided, including: S1: setting an initial bit error rate P.sub.e0 and an initial solution of correction factors; S2: randomly selecting a new solution of the correction factors from a proximinal subset of a current solution, and calculating a new bit error rate P.sub.enew; S3: determining whether the new bit error rate is smaller than a bit error rate of a previous decoding, and if so, receiving the new solution of the correction factors, otherwise calculating a reception probability based on a difference between the new bit error rate and the bit error rate of the previous decoding; S4: decreasing the initial bit error rate P.sub.e0 to determine whether a termination condition is satisfied, performing S5 if the termination condition is satisfied, otherwise performing S2; and S5: outputting a current solution of the correction factors as an optimal solution.