A method includes generating an extended result from a first operation circuitry having a result register bit width greater than a bus width associated with a residue check path of a second operation circuitry associated with a floating point unit. An extended result residue less a first portion residue of the extended result received from the residue check path is stored as a first partial result residue. The first partial result residue is compared with a first result residue of the second operation circuitry. The extended result residue less both the first partial result residue and a second portion residue of the extended result received from the residue check path as a second partial result residue is compared with a second result residue of the second operation circuitry.

A method includes generating an extended result from a first operation circuitry having a result register bit width greater than a bus width associated with a residue check path of a second operation circuitry associated with a floating point unit. An extended result residue less a first portion residue of the extended result received from the residue check path is stored as a first partial result residue. The first partial result residue is compared with a first result residue of the second operation circuitry. The extended result residue less both the first partial result residue and a second portion residue of the extended result received from the residue check path as a second partial result residue is compared with a second result residue of the second operation circuitry.

A method for iteratively decoding read bits in a solid state storage device. The read bits are encoded with a Q-ary LDPC code defined over a binary-extension Galois field GF(2.sup.r) and having length N. The method comprises determining a binary Tanner graph of the Q-ary LDPC code based on a Q-ary Tanner graph of the Q-ary LDPC code, and based on a binary coset representation of the Galois field GF(2.sup.r). The binary Tanner graph comprises, for each Q-ary variable node/Q-ary check node pair of the Q-ary Tanner graph, (2.sup.r-1) binary variable nodes each one being associated with a respective one of said cosets; (2.sup.r-1-r) binary parity-check nodes each one being connected to one or more of said (2.sup.r-1) binary variable nodes according to said binary coset representation of the Galois field GF(2.sup.r), wherein each binary parity-check node corresponds to a respective parity-check equation associated with a first parity-check matrix that results from said binary coset representation, and (2.sup.r-1) binary check nodes each one being connected to a respective one of said (2.sup.r-1) binary variable nodes according to a second parity-check matrix defining the Q-ary LDPC code. The method further comprises, based on a Majority-Logic decoding algorithm, mapping the read bits into N symbols each one including, for each bit thereof, a bit value and a reliability thereof, and providing each symbol of said N symbols to a respective Q-ary variable node, wherein each bit of said each symbol is provided to a respective one of the (2.sup.r-1) binary variable nodes of said respective Q-ary variable node. The method also comprises, based on the Majority-Logic decoding algorithm, iteratively performing the following steps: i) at each binary check node, determining a first bit estimate and a first bit reliability of each bit of the respective symbol according to, respectively, a second bit estimate and a second bit reliability of that bit that are determined at each binary variable node connected to that binary check node, and ii) at each binary variable node, updating the second bit estimate and the second bit reliability of each bit of the respective symbol based on the first bit estimate and the first bit reliability of that bit determined at each binary check node connected to that binary variable node, and based on the parity-check equation associated with the first parity-check matrix and corresponding to the parity-check node connected to that binary variable node.

The present disclosure relates to methods and systems for decoding a Bose-Chaudhuri-Hocquenghem (BCH) encoded codeword. The methods-may include receiving a codeword over a data channel; determining a plurality of syndrome values for the codeword during a first time interval; determining a set of initial elements during the first time interval; generating an error locator polynomial based on the plurality of syndrome values, the error locator polynomial representing one or more errors in the codeword; evaluating, based on the set of initial elements, the error locator polynomial to identify one or more error locations corresponding to the one or more errors in the codeword; and correcting the codeword based on the one or more error locations.

A method for iteratively decoding read bits in a solid state storage device. The read bits are encoded with a Q-ary LDPC code defined over a binary-extension Galois field GF(2.sup.r) and having length N. The method comprises determining a binary Tanner graph of the Q-ary LDPC code based on a Q-ary Tanner graph of the Q-ary LDPC code, and based on a binary coset representation of the Galois field GF(2.sup.r). The binary Tanner graph comprises, for each Q-ary variable node/Q-ary check node pair of the Q-ary Tanner graph, (2.sup.r-1) binary variable nodes each one being associated with a respective one of said cosets; (2.sup.r-1-r) binary parity-check nodes each one being connected to one or more of said (2.sup.r-1) binary variable nodes according to said binary coset representation of the Galois field GF(2.sup.r), wherein each binary parity-check node corresponds to a respective parity-check equation associated with a first parity-check matrix that results from said binary coset representation, and (2.sup.r-1) binary check nodes each one being connected to a respective one of said (2.sup.r-1) binary variable nodes according to a second parity-check matrix defining the Q-ary LDPC code. The method further comprises, based on a Majority-Logic decoding algorithm, mapping the read bits into N symbols each one including, for each bit thereof, a bit value and a reliability thereof, and providing each symbol of said N symbols to a respective Q-ary variable node, wherein each bit of said each symbol is provided to a respective one of the (2.sup.r-1) binary variable nodes of said respective Q-ary variable node. The method also comprises, based on the Majority-Logic decoding algorithm, iteratively performing the following steps: i) at each binary check node, determining a first bit estimate and a first bit reliability of each bit of the respective symbol according to, respectively, a second bit estimate and a second bit reliability of that bit that are determined at each binary variable node connected to that binary check node, and ii) at each binary variable node, updating the second bit estimate and the second bit reliability of each bit of the respective symbol based on the first bit estimate and the first bit reliability of that bit determined at each binary check node connected to that binary variable node, and based on the parity-check equation associated with the first parity-check matrix and corresponding to the parity-check node connected to that binary variable node.

The present disclosure relates to methods and systems for decoding a Bose-Chaudhuri-Hocquenghem (BCH) encoded codeword. The methods may include receiving a codeword over a data channel; determining a plurality of syndrome values for the codeword during a first time interval; determining a set of initial elements during the first time interval; generating an error locator polynomial based on the plurality of syndrome values, the error locator polynomial representing one or more errors in the codeword; evaluating, based on the set of initial elements, the error locator polynomial to identify one or more error locations corresponding to the one or more errors in the codeword; and correcting the codeword based on the one or more error locations.

A device includes a low density parity check (LDPC) decoder that is configured to receive a representation of a codeword. The LDPC decoder includes a circuit configured to set a message length of a decoding message at least partially based on an error metric associated with the representation of the codeword. The LDPC decoder also includes a processing unit including a first group of components and a second group of components. The processing unit configured to selectively couple the first group of components to the second group of components based on the message length of the decoding message.

A device includes a low density parity check (LDPC) decoder that is configured to receive a representation of a codeword. The LDPC decoder includes a circuit configured to set a message length of a decoding message at least partially based on an error metric associated with the representation of the codeword. The LDPC decoder also includes a processing unit including a first group of components and a second group of components. The processing unit configured to selectively couple the first group of components to the second group of components based on the message length of the decoding message.