Embodiments of the invention provide a variable node processing unit for a non-binary error correcting code decoder, the variable node processing unit being configured to receive one check node message and intrinsic reliability metrics, and to generate one variable node message from auxiliary components derived from said one check node message and intrinsic reliability metrics, the intrinsic reliability metrics being derived from a received signal, an auxiliary component comprising an auxiliary symbol and an auxiliary reliability metrics associated with said auxiliary symbol, wherein the variable node processing unit comprises: a sorting and redundancy elimination unit configured to process iteratively the auxiliary components and to determine components of the variable node message by iteratively sorting the auxiliary components according to a given order of the auxiliary reliability metrics and keeping a predefined number of auxiliary components comprising the auxiliary symbols that are the most reliable and all different from one another.

Reduced complexity decoders with improved error correction and related systems, methods, and apparatuses are disclosed. An apparatus includes an input terminal and a processing circuitry. The input terminal is provided at a physical layer device to receive, from a network, a low density parity check (LDPC) frame including bits. The bits correspond to log-likelihood ratio (LLR) messages indicating probabilities that the bits have predetermined logic values. The processing circuitry is to saturate LLR values of a portion of the LLR messages corresponding to known bits of the LDPC frame to a highest magnitude value represented by the LLR messages, and pass the LLR messages between check nodes and message nodes. The message nodes correspond to the bits. The check nodes correspond to parity check equations of a parity check matrix.

A sorting device and method for determining elementary check node components in an elementary check node processor implemented in a non-binary error correcting code decoder by sorting auxiliary components are presented. The auxiliary components are stored in a plurality of FIFO memories, each FIFO memory being assigned a FIFO number index. Each auxiliary component stored in a given FIFO memory comprises an auxiliary symbol, a reliability metrics representing the reliability of the auxiliary symbol, and the FIFO number index assigned to the given FIFO memory. The sorting device is configured to sort the auxiliary components by a plurality of multiplexers arranged sequentially. Each multiplexer is configured to initialize a candidate elementary check node component from the components of a FIFO memory corresponding to the auxiliary component which comprise the most reliable auxiliary symbol and to perform one or more iterations of the illustrated receiving, updating and sorting steps.

Embodiments of the invention provide an elementary check node processing unit (300) implemented in a check node processing unit of a non-binary error correcting code decoder, the elementary check node processing unit (300) being linked to a variable node processing unit (305) and being configured to receive a first message and a second message, each message comprising at least two components. The elementary check node processing unit (300) comprises a calculation unit (301) which determines two or more auxiliary components from the components comprised in the first message and from the components comprised in the second message, an auxiliary component comprising an auxiliary reliability metrics. The calculation unit (301) also determines, in association with each of the two or more auxiliary components, decoding performance values. The elementary check node processing unit (300) also comprises a selection unit (303) which selects, among the two or more auxiliary components, the auxiliary component that is associated with the optimal decoding performance values and determines an offset value from the auxiliary reliability metrics comprised in the selected auxiliary component. The elementary check node processing unit (300) then transmits the offset value and a selected set of auxiliary components among the two or more auxiliary components to the variable node processing unit (305).

Embodiments of the invention provide an elementary check node processing unit (300) implemented in a check node processing unit of a non-binary error correcting code decoder, the elementary check node processing unit (300) being linked to a variable node processing unit (305) and being configured to receive a first message and a second message, each message comprising at least two components. The elementary check node processing unit (300) comprises a calculation unit (301) which determines two or more auxiliary components from the components comprised in the first message and from the components comprised in the second message, an auxiliary component comprising an auxiliary reliability metrics. The calculation unit (301) also determines, in association with each of the two or more auxiliary components, decoding performance values. The elementary check node processing unit (300) also comprises a selection unit (303) which selects, among the two or more auxiliary components, the auxiliary component that is associated with the optimal decoding performance values and determines an offset value from the auxiliary reliability metrics comprised in the selected auxiliary component. The elementary check node processing unit (300) then transmits the offset value and a selected set of auxiliary components among the two or more auxiliary components to the variable node processing unit (305).

Reduced complexity decoders with improved error correction and related systems, methods, and apparatuses are disclosed. An apparatus includes an input terminal and a processing circuitry. The input terminal is provided at a physical layer device to receive, from a network, a low density parity check (LDPC) frame including bits. The bits correspond to log-likelihood ratio (LLR) messages indicating probabilities that the bits have predetermined logic values. The processing circuitry is to saturate LLR values of a portion of the LLR messages corresponding to known bits of the LDPC frame to a highest magnitude value represented by the LLR messages, and pass the LLR messages between check nodes and message nodes. The message nodes correspond to the bits. The check nodes correspond to parity check equations of a parity check matrix.

A sorting device for determining elementary check node components in an elementary check node processor (3) implemented in a non-binary error correcting code decoder by sorting auxiliary components. The auxiliary components are stored in a plurality of FIFO memories (33-n), each FIFO memory (33-n) being assigned a FIFO number index. Each auxiliary component stored in a given FIFO memory (33-n) comprises an auxiliary symbol, a reliability metrics representing the reliability of the auxiliary symbol, and the FIFO number index assigned to the given FIFO memory (33-n). The sorting device is configured to sort the auxiliary components by a plurality of multiplexers (34-m) arranged sequentially. Each multiplexers (34-m) is configured to initialize a candidate elementary check node component from the components of a FIFO memory corresponding to the auxiliary component which comprise the most reliable auxiliary symbol and to perform one or more iterations of the following steps: receive an auxiliary component extracted from the FIFO memory (33-n) which is assigned the FIFO number index comprised in the candidate elementary check node component determined at the previous iteration which comprises the most reliable candidate symbol, and update the candidate elementary check node component determined at the previous iteration by selecting one component among the received auxiliary component, the candidate elementary check node component determined at the previous iteration by the multiplexer (34-m), and the candidate elementary check node component determined at the previous iteration by the subsequent multiplexer (34-(m+1)).

The sorting device is configured to determine, at each of the one or more iterations, an elementary check node component by selecting the candidate elementary check node component which comprises the most reliable candidate symbol.

Embodiments of the invention provide a variable node processing unit (31) for a non-binary error correcting code decoder, the variable node processing unit (31) being configured to receive one check node message and intrinsic reliability metrics, and to generate one variable node message from auxiliary components derived from said one check node message and intrinsic reliability metrics, the intrinsic reliability metrics being derived from a received signal, an auxiliary component comprising an auxiliary symbol and an auxiliary reliability metrics associated with said auxiliary symbol, wherein the variable node processing unit (31) comprises: a sorting and redundancy elimination unit (313) configured to process iteratively the auxiliary components and to determine components of the variable node message by iteratively sorting the auxiliary components according to a given order of the auxiliary reliability metrics and keeping a predefined number of auxiliary components comprising the auxiliary symbols that are the most reliable and all different from one another.

A decoder is configured to perform, for a unit of data received by the decoder, a plurality of decoding iterations in which a plurality of messages are passed between a plurality of check nodes and a plurality of variable nodes, each message indicating a degree of reliability in an observed outcome of data. The decoder determines, for each of the plurality of decoding iterations, whether a trigger condition is satisfied based on an internal state of the decoder and, when a trigger condition is determined to be satisfied during a respective decoding iteration, scales one or more respective messages of the plurality of messages during a subsequent decoding iteration. The unit of data is decoded based on the plurality of decoding iterations and at least one scaled message resulting from the trigger condition being satisfied during the respective decoding iteration.

A decoder is configured to perform, for a unit of data received by the decoder, a plurality of decoding iterations in which a plurality of messages are passed between a plurality of check nodes and a plurality of variable nodes, each message indicating a degree of reliability in an observed outcome of data. The decoder determines, for each of the plurality of decoding iterations, whether a trigger condition is satisfied based on an internal state of the decoder and, when a trigger condition is determined to be satisfied during a respective decoding iteration, scales one or more respective messages of the plurality of messages during a subsequent decoding iteration. The unit of data is decoded based on the plurality of decoding iterations and at least one scaled message resulting from the trigger condition being satisfied during the respective decoding iteration.