Current Wireless transmission volume is such that techniques to compress transmitted data is the object of ongoing technical enhancements. The Invention consists of methods of using rapid changes in signal voltage to convey additional data which may be used for Data Compression, Encryption, and other purposes. They include varying amounts of change referred to as Encode Amplitude (EA) and Baseline Modulation (BM) using a change down to baseline voltage,

An encoder includes a low-pass filter to filter input audio signals. The low-pass filter has fixed filter coefficients. The encoder generates quantized signals based on a difference signal. The encoder includes an adaptive quantizer and a decoder to generate feedback signals. The decoder has an inverse quantizer and a predictor. The predictor has fixed control parameters which are based on a frequency response of the low-pass filter. The predictor may include a finite impulse response filter having fixed filter coefficients. The decoder may include an adaptive noise shaping filter coupled between the low-pass filter and the encoder. The adaptive noise shaping filter flattens signals within a frequency spectrum corresponding to a frequency spectrum of the low-pass filter.

A tracking analog-to-digital converter (ADC) for a power converter includes a first tracking loop and a second tracking loop. The first tracking loop is configured to track a voltage input to the tracking ADC using one or more comparators and has a re-clocking circuit to mitigate the impact of comparator output metastability, but introduces multi-cycle latency which increases a residual error of the voltage tracking provided by the first tracking loop. The second tracking loop is configured to supplement the voltage tracking provided by the first tracking loop and to reduce the residual error of the voltage tracking for dynamic changes at the voltage input. The second tracking loop has a single-cycle latency and is implemented with logic that is less sensitive to logic errors due to comparator metastability. Corresponding methods of voltage tracking and an electronic system are also described.

A tracking analog-to-digital converter (ADC) for a power converter includes a first tracking loop and a second tracking loop. The first tracking loop is configured to track a voltage input to the tracking ADC using one or more comparators and has a re-clocking circuit to mitigate the impact of comparator output metastability, but introduces multi-cycle latency which increases a residual error of the voltage tracking provided by the first tracking loop. The second tracking loop is configured to supplement the voltage tracking provided by the first tracking loop and to reduce the residual error of the voltage tracking for dynamic changes at the voltage input. The second tracking loop has a single-cycle latency and is implemented with logic that is less sensitive to logic errors due to comparator metastability. Corresponding methods of voltage tracking and an electronic system are also described.

In an embodiment, a method includes: receiving an audio frame; decomposing the received audio frame into M sub-band pulse-code modulation (PCM) audio frames, where M is a positive integer number; predicting a PCM sample of one sub-band PCM audio frame of the M sub-band PCM audio frames; comparing the predicted PCM sample with a corresponding received PCM sample to generate a prediction error sample; comparing an instantaneous absolute value of the prediction error sample with a threshold; and replacing the corresponding received PCM sample with a value based on the predicted PCM sample when the instantaneous absolute value of the prediction error sample is greater than the threshold.

Systems and methods for low power sample rate conversion are based on a noise shaping technique. A sample rate conversion circuit includes a clock synchronization circuit configured to receive an input sample sequence at a first sample rate and generate a valid sample sequence that is sampled at a second sample rate different from the first sample rate. The valid sample sequence may include valid samples from a registered sequence sampled at an oversampled rate greater than the first sample rate with invalid samples in the registered sequence being excluded from the valid sample sequence. The sample rate conversion circuit also includes a noise shaping circuit coupled to the clock synchronization circuit and configured to encode the valid sample sequence into a noise-shaped output sequence at the second sample rate by suppressing quantization noise from the valid sample sequence.

In an embodiment, a method includes: receiving an audio frame; decomposing the received audio frame into M sub-band pulse-code modulation (PCM) audio frames, where M is a positive integer number; predicting a PCM sample of one sub-band PCM audio frame of the M sub-band PCM audio frames; comparing the predicted PCM sample with a corresponding received PCM sample to generate a prediction error sample; comparing an instantaneous absolute value of the prediction error sample with a threshold; and replacing the corresponding received PCM sample with a value based on the predicted PCM sample when the instantaneous absolute value of the prediction error sample is greater than the threshold.

In an embodiment, a method includes: receiving an audio frame; decomposing the received audio frame into M sub-band pulse-code modulation (PCM) audio frames, where M is a positive integer number; predicting a PCM sample of one sub-band PCM audio frame of the M sub-band PCM audio frames; comparing the predicted PCM sample with a corresponding received PCM sample to generate a prediction error sample; comparing an instantaneous absolute value of the prediction error sample with a threshold; and replacing the corresponding received PCM sample with a value based on the predicted PCM sample when the instantaneous absolute value of the prediction error sample is greater than the threshold.

A source device comprising a memory and a processor may be configured to perform techniques described in this disclosure. The memory may store at least a portion of the audio data. The processor may obtain, from a compressed version of the audio data, a symbol, and obtain a plurality of intervals, each having a same bit length. The processor may obtain a portion of the symbol within the bit length and an excess portion of the symbol over the bit length, and specify, in a first interval, the portion of the symbol. The processor may also specify, in a second interval, the excess portion of the symbol, and apply, to the first interval and the second interval, error resiliency. The processor may specify, in a bitstream representative of the compressed version of the audio data, the first error resilient interval and the second error resilient interval.

An encoder includes a low-pass filter to filter input audio signals. The low-pass filter has fixed filter coefficients. The encoder generates quantized signals based on a difference signal. The encoder includes an adaptive quantizer and a decoder to generate feedback signals. The decoder has an inverse quantizer and a predictor. The predictor has fixed control parameters which are based on a frequency response of the low-pass filter. The predictor may include a finite impulse response filter having fixed filter coefficients. The decoder may include an adaptive noise shaping filter coupled between the low-pass filter and the encoder. The adaptive noise shaping filter flattens signals within a frequency spectrum corresponding to a frequency spectrum of the low-pass filter.