An impedance sensing circuit includes first and second current sources and first and second bias current sources that are appropriately coupled to first and second resistors. The impedance sensing circuit also includes a comparator that compares a first voltage based on the first terminal of the first resistor to a second voltage based on the first terminal of the second resistor to generate a comparator output signal. Either the comparator output signal or a digital signal based on the comparator output signal operates to regulate the current signals output from the first and second current sources so that the first voltage is same as the second voltage. The comparator output signal and the digital signal is representative of a difference between the first voltage and the second voltage that is based on an impedance difference between the first resistor and the second resistor.

A sensor device includes an A/D converter including an adder that computes a difference between an analog input signal and a predicted value, the adder includes a capacitive adder defined by a series circuit including a capacitive charge output device and a capacitor. A capacitive component in the charge output device defines a portion of the capacitance of the capacitive adder. A digital prediction filter generates the predicted value based on an output from a quantizer. The capacitive adder computes the difference between the analog input signal from the charge output device and the predicted value. The quantizer quantizes and encodes the difference. The A/D converter performs a Δ modulation on the analog input signal which is converted into a digital signal.

Radio-frequency (RF) receivers having bandpass sigma-delta analog sigma analog-to-digital converters (ADC) designed to digitize signals in the RF domain are described. Such bandpass ADCs utilize one or more of the following techniques to enhance noise immunity and reduce power consumption: generation of in-phase (I) and quadrature (Q) paths in the digital domain, n.sup.th order resonant bandpass filtering with n>1, and signal sub-sampling in an i.sup.th Nyquist zone with i>1. Compared to RF receivers in which the I and Q paths are generated in the analog domain, these RF receivers exhibit higher IRRs because they are not susceptible to in-phase/quadrature (IQ) mismatch. Using n.sup.th order resonant bandpass filtering with n>1 attenuates unwanted image tones. The bandpass ADC-based RF receivers described herein exhibit enhanced immunity to noise, achieving for example image rejection ratios (IRR) in excess of 95 dB.

An integrated circuit having multiple switched-capacitor delta-sigma data converter circuits includes compensation for voltage reference error due to leakage current that causes reference voltage droop. The reference filter capacitor terminal voltage is maintained by periodic connection to the reference feedback capacitor(s) that are alternately connected to a voltage reference buffer, and the leakage into the reference feedback capacitor networks of disabled converter circuits causes reference voltage droop. The compensation is either determined from the number of converter circuits that are disabled, or from an error between the filter capacitor voltage and a separate voltage reference, and may be applied by adjusting a resistance selectively coupled between the voltage reference buffer output and the filter capacitor, feedback applied to the voltage reference buffer or its input source. Alternatively, or in combination, correction may be applied to the output of the active converters by digital adjustment of output values.

The invention relates to an analog-to-digital converter (ADC). The objective of the invention to have an analog-to-digital converter with the capability of non-equidistant sample time spacing and minimizing energy consumption will be solved by an apparatus comprising a sigma-delta modulator and a sample-time-counter, both controlled by a sample clock, a next-sample-time-computation unit configured to compute a sample-time-counter value when a next digital output sample is requested, a sample-computation-trigger unit connected to the next-sample-time-computation unit configured to compare an actual sample-time-counter value with the sample-time-counter value when the next digital output sample is requested and to trigger a computation unit for calculating a next digital sample when requested and by powering off the sigma-delta modulator in intervals where its delivered samples are not used for any computed decimator output sample. The objective is also solved by a method using the aforementioned analog-to-digital converter.

An analog to digital converter (ADC) that is configured to service a photo-diode includes a capacitor and a self-referenced latched comparator. The capacitor produces a photo-diode voltage based on charging by a photo-diode current associated with the photo-diode and a digital to analog converter (DAC) source current and/or a DAC sink current. The self-referenced latched comparator generates a first digital signal that is based on a difference between the photo-diode voltage and a threshold voltage associated with the self-referenced latched comparator. Also, one or more processing modules executes operational instructions to process the first digital signal to generate a second digital signal and/or a third digital signal. An N-bit DAC generates the DAC source current based on the second digital signal, and an M-bit DAC generates the DAC sink current based on the third digital signal. The DAC source current and/or the DAC sink current tracks the photo-diode current.

An analog to digital converter (ADC) that is configured to service a photo-diode includes a capacitor and a self-referenced latched comparator. The capacitor produces a photo-diode voltage based on charging by a photo-diode current associated with the photo-diode and a digital to analog converter (DAC) source current and/or a DAC sink current. The self-referenced latched comparator generates a first digital signal that is based on a difference between the photo-diode voltage and a threshold voltage associated with the self-referenced latched comparator. Also, one or more processing modules executes operational instructions to process the first digital signal to generate a second digital signal and/or a third digital signal. An N-bit DAC generates the DAC source current based on the second digital signal, and an M-bit DAC generates the DAC sink current based on the third digital signal. The DAC source current and/or the DAC sink current tracks the photo-diode current.

The invention relates to an analog-to-digital converter (ADC). The objective of the invention to have an analog-to-digital converter with the capability of non-equidistant sample time spacing and minimizing energy consumption will be solved by an apparatus comprising a sigma-delta modulator and a sample-time-counter, both controlled by a sample clock, a next-sample-time-computation unit configured to compute a sample-time-counter value when a next digital output sample is requested, a sample-computation-trigger unit connected to the next-sample-time-computation unit configured to compare an actual sample-time-counter value with the sample-time-counter value when the next digital output sample is requested and to trigger a computation unit for calculating a next digital sample when requested and by powering off the sigma-delta modulator in intervals where its delivered samples are not used for any computed decimator output sample. The objective is also solved by a method using the aforementioned analog-to-digital converter.

An integrated circuit having multiple switched-capacitor delta-sigma data converter circuits includes compensation for voltage reference error due to leakage current that causes reference voltage droop. The reference filter capacitor terminal voltage is maintained by periodic connection to the reference feedback capacitor(s) that are alternately connected to a voltage reference buffer, and the leakage into the reference feedback capacitor networks of disabled converter circuits causes reference voltage droop. The compensation is either determined from the number of converter circuits that are disabled, or from an error between the filter capacitor voltage and a separate voltage reference, and may be applied by adjusting a resistance selectively coupled between the voltage reference buffer output and the filter capacitor, feedback applied to the voltage reference buffer or its input source. Alternatively, or in combination, correction may be applied to the output of the active converters by digital adjustment of output values.

A system and method of replicating and cancelling chopping folding error in delta-sigma modulators. The modulator may include a loop filter coupled to a quantizer providing a digital signal, chopper circuitry that chops analog signals of the loop filter at a chopping frequency, and chopping folding error cancellation circuitry that replicates and cancels a chopping folding error of the chopper circuitry to provide a corrected digital signal. A digital chopper or multiplier chops the digital signal to provide a chopped digital signal, and the chopped digital signal is either amplified or multiplied by a gain value or digitally filtered to replicate the chopping folding error, which is then subtracted from the digital signal for correction. The timing and duty cycle of the chopping frequency may be adjusted. Timing and duty cycle adjustment may be calibrated along with the filtering.