A circuit includes a transconductance stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output, and the second input is coupled to the second output. The comparator includes first through fifth transistors and a pair of cross-coupled transistors. The pair of cross-coupled transistors is coupled to the second current terminals of the first and second transistors. The second current terminal of the third transistor is coupled to the second current terminal of the first transistor, and the first current terminals of the first, second, and third transistors are coupled together. The second current terminals of the fourth and fifth transistors are coupled together and to the control input of the third transistor.

A digital signal generation assumes that a base frequency (the frequency with which the primitive phase angles are specified relative to) is equal to the carrier frequency for all relevant times. But this causes errors in the digital signals output to each array element transducer. Thus, it is necessary for the development of a signal generation system that is capable of producing a digital signal using the free selection of amplitude and phase. This is used to produce a substantially error-free signal that preserves the amplitude and phase relative to a constant base frequency while allowing the carrier frequency to vary.

A digital signal generation assumes that a base frequency (the frequency with which the primitive phase angles are specified relative to) is equal to the carrier frequency for all relevant times. But this causes errors in the digital signals output to each array element transducer. Thus, it is necessary for the development of a signal generation system that is capable of producing a digital signal using the free selection of amplitude and phase. This is used to produce a substantially error-free signal that preserves the amplitude and phase relative to a constant base frequency while allowing the carrier frequency to vary.

A digital signal generation assumes that a base frequency (the frequency with which the primitive phase angles are specified relative to) is equal to the carrier frequency for all relevant times. But this causes errors in the digital signals output to each array element transducer. Thus, it is necessary for the development of a signal generation system that is capable of producing a digital signal using the free selection of amplitude and phase. This is used to produce a substantially error-free signal that preserves the amplitude and phase relative to a constant base frequency while allowing the carrier frequency to vary.

A digital signal generation assumes that a base frequency (the frequency with which the primitive phase angles are specified relative to) is equal to the carrier frequency for all relevant times. But this causes errors in the digital signals output to each array element transducer. Thus, it is necessary for the development of a signal generation system that is capable of producing a digital signal using the free selection of amplitude and phase. This is used to produce a substantially error-free signal that preserves the amplitude and phase relative to a constant base frequency while allowing the carrier frequency to vary.

A circuit includes a transconductance stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output, and the second input is coupled to the second output. The comparator includes first through fifth transistors and a pair of cross-coupled transistors. The pair of cross-coupled transistors is coupled to the second current terminals of the first and second transistors. The second current terminal of the third transistor is coupled to the second current terminal of the first transistor, and the first current terminals of the first, second, and third transistors are coupled together. The second current terminals of the fourth and fifth transistors are coupled together and to the control input of the third transistor.

A digital signal generation assumes that a base frequency (the frequency with which the primitive phase angles are specified relative to) is equal to the carrier frequency for all relevant times. But this causes errors in the digital signals output to each array element transducer. Thus, it is necessary for the development of a signal generation system that is capable of producing a digital signal using the free selection of amplitude and phase. This is used to produce a substantially error-free signal that preserves the amplitude and phase relative to a constant base frequency while allowing the carrier frequency to vary.

A circuit includes a transconductance stage having first and second outputs. The circuit also includes a comparator having first and second inputs. The first input is coupled to the first output, and the second input is coupled to the second output. The comparator includes first through fifth transistors and a pair of cross-coupled transistors. The pair of cross-coupled transistors is coupled to the second current terminals of the first and second transistors. The second current terminal of the third transistor is coupled to the second current terminal of the first transistor, and the first current terminals of the first, second, and third transistors are coupled together. The second current terminals of the fourth and fifth transistors are coupled together and to the control input of the third transistor.

An arbitrary rate digital decimator filter (204) and associated method are disclosed for filtering a digital data stream with a plurality of cascaded power-of-two decimator stages (205, 207) connected to receive the digital data stream and to generate a first filtered digital signal which is provided to a fractional resampling stage (211) which generates a second filtered digital signal with delta-sigma modulator (310) and a limited integrator stage (320) connected to receive a first control (301) word and a feedback clock signal (305) with inserted or swallowed pulses which is generated by a clock generator in response to pulse commands generated by the limited integrator stage, wherein the limited integrator is configured to generate time shift commands (303) to a timing shift filter (340) which performs fractional interpolation on the first filtered digital signal to generate the second filtered digital signal.

A radio frequency system. In some embodiments, the system includes a one-bit receiver, and the one-bit receiver includes a digital pseudo random noise generator, a one-bit digital to analog converter, a power combiner, a one-bit analog to digital converter, and a digital subtraction circuit. The digital pseudo random noise generator produces a signal added to the received signal before analog to digital conversion. After analog to digital conversion, a delayed version of the dither is subtracted from the digital signal.