A sensor signal processing circuit including a delta-sigma analog-to-digital converter (ADC) and a control circuit is disclosed. The circuit is configured to adaptively activate one or more segments of current elements for sequential sampling periods based on a digital signal input to a DAC, wherein less than N current elements are allocated to each segment, each current element in an active segment is enabled and either contributes to a feedback signal of the DAC or does not contribute to the feedback signal, and current elements not in an active segment are disabled. The circuit can be integrated with an acoustic or other sensor as part of a sensor assembly.

An A/D converter includes: a sampler that includes a sampling capacitor and samples an input signal; a D/A converter that selectively outputs an analog voltage; an integrator that integrates an input from the sampler and an input from the D/A converter; Multiple switches that include a first switch independently connecting the sampler to the integrator, a second switch independently connecting the D/A converter to the integrator, a third switch, and, a fourth switch, a quantizer that quantizes an output of the integrator; a control circuit that outputs a digital value based on an output of the quantizer, and a reference potential generation circuit that provides a second reference potential to an integrator side of the sampler through the third switch and provides a first reference potential to the integrator side of the D/A converter through the fourth switch.

An A/D converter includes: a sampler that includes a sampling capacitor and samples an input signal; a D/A converter that selectively outputs an analog voltage; an integrator that integrates an input from the sampler and an input from the D/A converter; Multiple switches that include a first switch independently connecting the sampler to the integrator, a second switch independently connecting the D/A converter to the integrator, a third switch, and, a fourth switch, a quantizer that quantizes an output of the integrator; a control circuit that outputs a digital value based on an output of the quantizer, and a reference potential generation circuit that provides a second reference potential to an integrator side of the sampler through the third switch and provides a first reference potential to the integrator side of the D/A converter through the fourth switch.

Exemplary multipath digital microphone described herein can comprise exemplary embodiments of adaptive ADC range multipath digital microphones, which allow low power to be achieved for amplifiers or gain stages, as well as for exemplary adaptive ADCs in exemplary multipath digital microphone arrangements described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can comprise an exemplary glitch removal component configured to minimize audible artifacts associated with the change in the gain of the exemplary adaptive ADCs.

An apparatus comprises a sigma-delta analog-to-digital converter (ADC) circuit configured to convert an analog input signal to a digital value. The sigma-delta ADC circuit includes a loop filter circuit including at least one loop filter amplifier, a flash ADC circuit including multiple comparators, and a bias control circuit configured to change a biasing of the at least one loop filter amplifier according to outputs of the multiple comparators of the flash ADC circuit.

Methods and devices are described for controlling excess loop delay (ELD) gain compensation in a digital-to-analog converter (DAC) of a successive approximation register (SAR) analog-to-digital converter (ADC) by using DAC unit elements in the ELD DAC and DACs for the SAR ADC efficiently. The ELD DAC and DAC partially share DAC units (e.g. capacitors or current sources) to minimize total DAC units used to limit area and power usage while maintaining operational flexibility. Different configurations provide ELD gains of less than or greater than one. A dedicated sampling capacitor is also provided to allow flexible gain control by capacitance ratio.

Exemplary multipath digital microphone described herein can comprise exemplary embodiments of adaptive ADC range multipath digital microphones, which allow low power to be achieved for amplifiers or gain stages, as well as for exemplary adaptive ADCs in exemplary multipath digital microphone arrangements described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can comprise an exemplary glitch removal component configured to minimize audible artifacts associated with the change in the gain of the exemplary adaptive ADCs.

Exemplary multipath digital microphone described herein can comprise exemplary embodiments of adaptive ADC range multipath digital microphones, which allow low power to be achieved for amplifiers or gain stages, as well as for exemplary adaptive ADCs in exemplary multipath digital microphone arrangements described herein, while still providing a high DR digital microphone systems. Further non-limiting embodiments can comprise an exemplary glitch removal component configured to minimize audible artifacts associated with the change in the gain of the exemplary adaptive ADCs.

Embodiments of sigma-delta analog-to-digital converter (ADC) circuits and a microphone circuit are disclosed. In an embodiment, a sigma-delta ADC circuit includes a pair of operational transconductance amplifiers (OTAs), a filter connected to the pair of OTAs, a quantizer connected to the filter, a differential digital-to-analog converter (DAC) connected to the quantizer, and a bias compensation circuit configured to measure a biasing condition of a first OTA of the pair of OTAs and to apply the biasing condition of the first OTA to a second OTA of the pair of OTAs to reduce Total Harmonic Distortion Plus Noise (THD+N) in the sigma-delta ADC circuit. An output of a microphone and a differential output of the differential DAC are inputted into input terminals of the pair of OTAs.

A delta-sigma modulator including force circuitry that receives an output digital signal and provides a forced digital signal with a predetermined force state based on a force control signal, a combiner that subtracts the forced digital signal from the output digital signal for providing a digital error signal, and force correction circuitry that converts the digital error signal into one or more analog error correction signals applied to corresponding inputs of loop filter circuitry. The digital error signal and the force control signal may each be used to develop corresponding analog feedback signals used to adjust an analog input signal. The digital error signal may also be converted to one or more correction signals applied to corresponding inputs of the loop filter circuitry to correct the output digital signal. The digital error signal may also be used by a digital noise cancellation filter to further correct the output digital signal.