In accordance with an embodiment, a delta-sigma modulator includes: an analog loop filter comprising an outer portion and an inner portion having an input coupled to the outer portion; a quantizer coupled to an output of the inner portion of the analog loop filter; an outer feedback path coupled between an output of the quantizer and an input to the outer portion of the analog loop filter; and a compensation filter coupled between an output of the quantizer and an input of the inner portion of the analog loop filter. The compensation filter has a transfer function configured to correct for an effect of excess loop delay (ELD) on the delta-sigma modulator.

A receiver is described, the receiver comprising an ABB filter stage, an ADC stage. The ABB filter stage comprises an ABB filter stage input configured to receive an analog baseband, BB, signal and an ABB filter stage output configured to provide a filtered analog BB signal. The ADC stage comprises an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal. The ADC stage comprises an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital, A/D, conversion of the ADC input signal to derive the digital BB signal.

An idle tone dispersion device outputs a frequency delta-sigma modulation signal obtained by using either one of a reference signal and a measured signal to perform frequency delta-sigma modulation of the other and dispersing an idle tone. The idle tone dispersion device includes n (n is any natural number equal to or larger than 2) frequency delta-sigma modulation sections and an adder configured to add up output signals of the n frequency delta-sigma modulation sections and output the frequency delta-sigma modulation signal. Each of the n frequency delta-sigma modulation sections uses either one of the reference signal and the measured signal to perform the frequency delta-sigma modulation of the other. At least one of the reference signal and the measured signal includes jitter including a frequency component higher than a frequency of an idle tone of an output signal of the frequency delta-sigma modulation section.

An idle tone dispersion device outputs a frequency delta-sigma modulation signal obtained by using either one of a reference signal and a measured signal to perform frequency delta-sigma modulation of the other and dispersing an idle tone. The idle tone dispersion device includes n (n is any natural number equal to or larger than 2) frequency delta-sigma modulation sections and an adder configured to add up output signals of the n frequency delta-sigma modulation sections and output the frequency delta-sigma modulation signal. Each of the n frequency delta-sigma modulation sections uses either one of the reference signal and the measured signal to perform the frequency delta-sigma modulation of the other. At least one of the reference signal and the measured signal includes jitter including a frequency component higher than a frequency of an idle tone of an output signal of the frequency delta-sigma modulation section.

A current mode sigma-delta modulator comprises an input node; a comparator that compares a voltage of the input node to a reference voltage and outputs a comparison result; an integrating capacitor connected to an input of the comparator; and a switched capacitor circuit connected at a first end to the input node, the input of the comparator, and the integrating capacitor, and connected at a second end to an output of the comparator. The current mode sigma-delta modulator is a component of an analog-to-digital converter.

In accordance with an embodiment, a delta-sigma modulator includes: an analog loop filter comprising an outer portion and an inner portion having an input coupled to the outer portion; a quantizer coupled to an output of the inner portion of the analog loop filter; an outer feedback path coupled between an output of the quantizer and an input to the outer portion of the analog loop filter; and a compensation filter coupled between an output of the quantizer and an input of the inner portion of the analog loop filter. The compensation filter has a transfer function configured to correct for an effect of excess loop delay (ELD) on the delta-sigma modulator.

A digital to analog converter (DAC) circuit includes pulse generator circuit for generating voltage pulses having a predetermined length and shape. The voltage pulses are used to control the generation of current pulses generated by a voltage to current converter. The voltage to current converter includes a set of switchable resistors where the resistance value provided by the set is dependent upon a digital value of a digital signal. In some embodiments, the current amplitude of the current pulses is dependent upon the resistance value and is indicative of the digital value.

A signal processing circuit has a first signal loop with a first signal processing block and a first feedback path that extends around the first signal processing block, the first signal processing block having a frequency dependence that causes the first signal loop to generate a passband. A second signal processing block is downstream of the first signal loop. A second feedback path extends from downstream of the second signal processing block to upstream of the first signal processing block. In operation, the first feedback path reinforces a signal in the passband and the second feedback path conditions the signal at an output downstream of the first signal processing block.

A delta-sigma modulator includes a loop filter, a quantizer configured to change an analog output signal into a digital signal, and a digital-to-analog converter configured to receive the digital signal and including a first capacitor and a second capacitor. In a first sampling period, the first capacitor is discharged, and at the same time, the second capacitor is charged with a reference voltage. In a second sampling period, the digital signal includes noise caused by a clock jitter, the first capacitor is charged with a reference voltage, and the second capacitor is discharged and generates a charge corresponding to the noise. In a next first sampling period, the first capacitor is discharged, and at the same time, the second capacitor generates a noise current corresponding to the noise using the charge and is charged with a reference voltage.

A current mode sigma-delta modulator comprises an input node; a comparator that compares a voltage of the input node to a reference voltage and outputs a comparison result; an integrating capacitor connected to an input of the comparator; and a switched capacitor circuit connected at a first end to the input node, the input of the comparator, and the integrating capacitor, and connected at a second end to an output of the comparator. The current mode sigma-delta modulator is a component of an analog-to-digital converter.