A pulse width modulation (PWM) interleaving system is provided. The PWM interleaving system includes active harmonic filters (AHFs). The AHFs are disposed in parallel with each other and with a load. The AHFs are electrically coupled to a common coupling point that is electrically interposed between a grid and the load. The AHFs are configured to affect, by PWM, a characteristic of current flowing between the grid and the load. The PWM interleaving system further includes a controller operably coupled to the AHFs and configured to synchronize the PWMs of the AHFs to thereby cancel ripple currents propagating towards the grid.

A frequency ratio measurement device includes a counter section configured to count a time event of a first signal and output a count value obtained by multiplying the time event by k.sub.0, a time to digital converter section configured to output a time digital value corresponding to a phase difference between the first signal and a second signal, a combiner section configured to output a combined value of the count value and the time digital value, a subtractor section configured to output a difference value between a first value based on the combined value and a second value, a quantizer section configured to compare a third value based on the difference value with a predetermined threshold to thereby output a quantized value obtained by quantizing the third value, and a feedback section configured to output, based on a time event of the second signal, the second value based on the quantized value. The frequency ratio measurement device outputs, based on the quantized value, a delta-sigma modulated signal corresponding to a frequency ratio of the first signal and the second signal.

A receiver is described, the receiver comprising an ABB filter stage, an ADC stage. The ABB filter stage comprises an ABB filter stage input configured to receive an analog baseband, BB, signal and an ABB filter stage output configured to provide a filtered analog BB signal. The ADC stage comprises an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal. The ADC stage comprises an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital, A/D, conversion of the ADC input signal to derive the digital BB signal.

A frequency ratio measurement device includes a counter section configured to count a time event of a first signal and output a count value obtained by multiplying the time event by k.sub.0, a time to digital converter section configured to output a time digital value corresponding to a phase difference between the first signal and a second signal, a combiner section configured to output a combined value of the count value and the time digital value, a subtractor section configured to output a difference value between a first value based on the combined value and a second value, a quantizer section configured to compare a third value based on the difference value with a predetermined threshold to thereby output a quantized value obtained by quantizing the third value, and a feedback section configured to output, based on a time event of the second signal, the second value based on the quantized value. The frequency ratio measurement device outputs, based on the quantized value, a delta-sigma modulated signal corresponding to a frequency ratio of the first signal and the second signal.

A continuous time Delta-Sigma (CT-) modulator has an input node configured to receive an input signal and an output node configured to output a digital output signal. The CT- modulator includes a feedback loop with a summation circuit configured to sum the digital output signal with a jitter perturbed test signal to generate a signal supplied to an input of a digital to analog converter circuit. A single tone signal is injected with a jitter error of a clock signal to generate the jitter perturbed test signal. A processing circuit processes the digital output signal to detect a signal to noise ratio of the CT- modulator. The detected signal to noise ratio is indicative of presence of jitter in the clock signal.

A receiver is described, the receiver comprising an ABB filter stage, an ADC stage. The ABB filter stage comprises an ABB filter stage input configured to receive an analog baseband, BB, signal and an ABB filter stage output configured to provide a filtered analog BB signal. The ADC stage comprises an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal. The ADC stage comprises an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital, A/D, conversion of the ADC input signal to derive the digital BB signal.

A pulse width modulation (PWM) interleaving system is provided. The PWM interleaving system includes active harmonic filters (AHFs). The AHFs are disposed in parallel with each other and with a load. The AHFs are electrically coupled to a common coupling point that is electrically interposed between a grid and the load. The AHFs are configured to affect, by PWM, a characteristic of current flowing between the grid and the load. The PWM interleaving system further includes a controller operably coupled to the AHFs and configured to synchronize the PWMs of the AHFs to thereby cancel ripple currents propagating towards the grid.

A phased-locked loop (PLL) includes a first oscillator supplying a first oscillator signal with a first jitter component and a second oscillator supplying a second oscillator signal with a second jitter component. The second jitter component is higher than the first jitter component. A selector circuit selects either the first oscillator signal or the second oscillator signal as the PLL output signal. The first oscillator signal and the second oscillator signal may have different frequencies with the lower frequency signal having more jitter. The oscillator producing the signal with less jitter utilizes more power. A continuous time delta-sigma modulator analog-to-digital converter (ADC) receives the PLL output signal as an input clock signal. A high gain setting of an amplifier supplying an input signal to the ADC selects a lower jitter signal input clock signal and a lower gain setting selects a higher jitter input clock signal.

A receiver is described, the receiver comprising an ABB filter stage, an ADC stage. The ABB filter stage comprises an ABB filter stage input configured to receive an analog baseband, BB, signal and an ABB filter stage output configured to provide a filtered analog BB signal. The ADC stage comprises an ADC stage input configured to receive the filtered analog BB signal and an ADC stage output configured to provide a digital BB signal. The ADC stage comprises an ADC comprising an ADC input configured to receive the filtered analog BB signal or a signal derived therefrom as an ADC input signal, and wherein the ADC is configured to perform an analog-to-digital, A/D, conversion of the ADC input signal to derive the digital BB signal.

A continuous time Delta-Sigma (CT-) modulator has an input node configured to receive an input signal and an output node configured to output a digital output signal. The CT- modulator includes a feedback loop with a summation circuit configured to sum the digital output signal with a jitter perturbed test signal to generate a signal supplied to an input of a digital to analog converter circuit. A single tone signal is injected with a jitter error of a clock signal to generate the jitter perturbed test signal. A processing circuit processes the digital output signal to detect a signal to noise ratio of the CT- modulator. The detected signal to noise ratio is indicative of presence of jitter in the clock signal.