A tracking ADC with adaptive slew rate boosting can dynamically adjust one or more of its operational parameters in response to detecting a slew rate limit condition. In some embodiments, slew rate boosting can include increasing the value of a digital error signal in response to detection of a slew rate limit condition. In other embodiments, slew rate boosting can include increasing a clock frequency of the tracking ADC in response to detection of a slew rate limit condition.

A delta-sigma modulator includes a first amplifier having an input, a feedback control input, and an output. The input is a first input of the delta-sigma modulator. The delta-sigma modulator further includes a first integrator and a first quantizer. The first integrator has an input and an output. The output of the first amplifier is coupled to the input of the first integrator. The first quantizer has an input and an output. The output of the first quantizer is coupled to the feedback control input of the first amplifier.

A delta-sigma modulator includes a first amplifier having an input, a feedback control input, and an output. The input is a first input of the delta-sigma modulator. The delta-sigma modulator further includes a first integrator and a first quantizer. The first integrator has an input and an output. The output of the first amplifier is coupled to the input of the first integrator. The first quantizer has an input and an output. The output of the first quantizer is coupled to the feedback control input of the first amplifier.

A differential output current digital-to-analog converter (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and an output impedance coupled between the pair of output terminals such that the output impedance is in parallel with the load.

A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and a plurality of warming switches, each warming switch coupled to a respective bias transistor of a respective DAC element of the plurality of DAC elements, wherein the control circuit may further be configured to selectively control each such warming switch in order to selectively de-bias and bias a respective bias transistor of such warming switch when a respective DAC element of the respective bias transistor is output-disabled from generating the differential output current signal.

A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and a plurality of warming switches, each warming switch coupled to a respective bias transistor of a respective DAC element of the plurality of DAC elements, wherein the control circuit may further be configured to selectively control each such warming switch in order to selectively de-bias and bias a respective bias transistor of such warming switch when a respective DAC element of the respective bias transistor is output-disabled from generating the differential output current signal.

A differential output current digital-to-analog (IDAC) circuit may include a delta-sigma modulator configured to receive a digital input signal, a control circuit responsive to the delta-sigma modulator configured to perform a DAC decode operation, a plurality of DAC elements responsive to the DAC decode operation, the plurality of DAC elements configured to, in concert, generate a differential output current signal based on the digital input signal to a load coupled to a pair of output terminals of the IDAC, and an output impedance coupled between the pair of output terminals such that the output impedance is in parallel with the load.

A system may include a current digital-to-analog converter (IDAC) configured to convert a digital input signal into an output current signal and a switched-mode power supply configured to provide electrical energy in the form of a supply voltage to the IDAC for operation of the IDAC, the switched-mode power supply configured to track a voltage signal derived from the digital input current signal and generate the supply voltage based on the voltage signal and a voltage headroom above the voltage signal.

A system may include a current digital-to-analog converter (IDAC) configured to convert a digital input signal into an output current signal and a switched-mode power supply configured to provide electrical energy in the form of a supply voltage to the IDAC for operation of the IDAC, the switched-mode power supply configured to track a voltage signal derived from the digital input current signal and generate the supply voltage based on the voltage signal and a voltage headroom above the voltage signal.

A continuous-time analog-to-digital converter (ADC) includes a plurality of integrators selectively coupled in series. The ADC may further include a quantizer with excess loop delay (ELD) compensation. The quantizer may be coupled in series to a least one integrator. The ELD compensation may be programmable based on a transfer function of the ADC. The ADC may further include parallel digital-to-analog converters (DACs). Each DAC may have an input coupled to an output of the quantizer, and an output coupled to an input of a corresponding integrator. The ADC may further include a bypass path coupled to an input or output of one of the integrators. The bypass path may be configured to selectively bypass one or more of the integrators to change the transfer function of the ADC.