A digital phase-locked loop (DPLL) may include a time-to-digital converter (TDC) to provide a phase error signal, a frequency-divider to perform frequency division on an output signal to generate a frequency-divided output signal, a delta-sigma-modulator (DSM) to provide a test signal that represents a quantization error of the DSM, and a digital-to-time converter (DTC) to at least partially remove the quantization error from the frequency-divided output signal based on the test signal to generate the feedback signal. The DPLL may include a circuit to cause the DTC to provide a percentage of the quantization error such that the percentage of the quantization error is in the phase error signal, and a TDC calibration component to calibrate the TDC by applying a gain adjustment factor to the TDC. The gain adjustment factor may be based on the test signal and the phase error signal including the percentage of the quantization error.

Apparatus includes an ADC configured to convert an analog signal to a digital signal, a comparator having a first input responsive to the analog signal, a second input responsive to the digital signal, and an output at which a comparison signal is provided, and an output checker configured to process the comparison signal to generate a fault signal indicative of whether a fault has occurred in the ADC. The comparator can be an analog comparator in which case the digital signal is converted to an analog signal for the comparison or a digital comparator in which case an additional ADC is provided to convert the analog signal into a digital signal for the comparison. Embodiments include more than one ADC in which case summation elements are provided to sum the analog signals and the digital signals for the comparison.

A calibratable switched-capacitor voltage reference and an associated calibration method are described. The voltage reference includes dynamic diode elements providing diode voltages, input capacitor(s) for sampling input voltages, base-emitter capacitor(s) for sampling one diode voltage with respect to a ground, dynamically trimmable capacitor(s) for sampling the one diode voltage with respect to another diode voltage, and an operational amplifier coupled to the capacitors for providing reference voltage(s) based on the sampled input and diode voltages and on trims of the trimmable capacitor(s). The voltage reference can be configured as a first integrator of a modulator stage of a delta-sigma analog-to-digital converter.

An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multi-bit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.

A method for testing an analog-to-digital converter unit, which is equipped to convert an analog input signal into a digital output signal with the aid of delta-sigma modulation. The method includes: generating an analog input signal; applying a predefined interference signal to the analog input signal and storing the resulting digital output signal as test result; determining that a fault is present if a transfer function of the analog-to-digital converter unit, which is ascertained from the test result and the input signal, has a deviation from a predefined target transfer function that is greater than a predefined reference value, a fault signal being output if a fault is determined.

A delta-sigma modulator is provided with: a loop filter 30; a quantizer 36 that generates quantized data on the basis of an output from the loop filter 30; an internal path 42 connected to the loop filter 30 or the quantizer 36; and a compensator 38 that provides, to the internal path 42, a compensation signal for compensating for distortion that occurs in a frequency component at a target frequency, the frequency component being among frequency components of a pulse train corresponding to the quantized data.

A signal processing circuit includes: a plurality of A/D conversion units of a plurality of channels, each of plurality of the A/D conversion units including an amplifier configured to amplify an input analog signal and an A/D converter configured to convert an output signal from the amplifier into a digital signal, wherein at least one of operation parameters of the amplifier and the A/D converter is set individually for each of the plurality of channels.

A built-in self-test (BIST) circuit is provided for testing an analog-to-digital converter (ADC). A multi-order sigma-delta (ΣΔ) modulator has an input that receives an input signal, a first output generating analog test signal derived from the input signal and applied to an input of the ADC and a second output generating a binary data stream. A digital recombination and filtering circuit has a first input that receives the binary data stream and a second input that receives a digital test signal output from the ADC in response to the analog test signal. The digital recombination and filtering circuit combines and filters the binary data stream and digital test signal to generate a digital result signal including a signal component derived from an error introduced by operation of the ADC. A correlation circuit is used to isolate that error signal component.

A built-in-self-test (BIST) circuit is connected to a processor and a sigma-delta modulator (SDM) and includes an averaging circuit, a reference signal generator, and a comparator. The averaging circuit calculates an average of a sum of a set of bit signals of the SDM output signal over a period of time period, and generates an average SDM signal. The reference signal generator generates a reference SDM signal based on an SDM input signal. The comparator compares the voltage levels of the average SDM and reference SDM signals with a threshold value, and generates a test output signal based on the comparison.

A method for monitoring a power electronic assembly is improved to be more effective and versatile. It includes converting and/or modifying an electrical input into at least one electrical output by a conversion and/or modifying process which proceeds in connection with the power electronic assembly. During the conversion and/or modification a bit stream is generated by a delta-sigma modulator and represents the electrical value, that is to say the electrical input or the at least one electrical output. One bit stream each can also be generated by a plurality of delta-sigma modulators and represents the respective electrical value, that is to say the electrical input and the at least one electrical output. The power electronic assembly is monitored based on the one bit stream(s) thus generated and available as a result. The bit stream(s) is/are not demodulated, and therefore very meaningful information of the corresponding useful signal is provided.