A delay chain circuit with series coupled delay elements receives a reference clock signal and outputs phase-shifted clock signals. A multiplexer circuit receives the phase-shifted clock signals and selects among the phase-shifted clock signals for output as in response to a selection signal. The selection signal is generated by a control circuit from a periodic signal having a triangular wave profile. A sigma-delta modulator converts the periodic signal to a digital signal, and an integrator circuit integrates the digital signal to output the selection signal. The selected phase-shifted clock signal is applied as the reference signal to a phase locked loop which generates a spread spectrum clock signal.

A quad signal generator circuit generates four 2.sup.N-1 bit control signals in response to a 2.sup.N-1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2.sup.N-1 unit DAC elements, with each unit DAC element including four switching circuits controlled by corresponding bits of the four 2.sup.N-1 bit control signals. Outputs of the 2.sup.N-1 unit DAC elements are summed to generate an analog output signal. The quad signal generator circuit controls a time delay applied to clock signals relative to the 2.sup.N-1 bit thermometer coded signal and a time delay applied to the 2.sup.N-1 bit thermometer coded signal relative to the delayed clock signals in logically generating the four 2.sup.N-1 bit control signals. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2.sup.N-1 bit thermometer coded signal.

A delta-sigma modulator includes a first integrator and a comparator. The comparator's positive input couples to the first integrator's positive output, and the comparator's negative input couples to the first integrator's negative output. A first current DAC comprises a current source device, and first and second transistors. The first transistor has a first transistor control input and first and second current terminals. The first current terminal couples to the current source device, and the second current terminal couples to the first integrator positive output. The second transistor has a second transistor control input and third and fourth current terminals. The third current terminal couples to the current source device, and the fourth current terminal couples to the first integrator negative output. A first capacitive device couples to the second transistor control input and to both the second current terminal and the first integrator positive output.

An Integrated Circuit (IC) includes feedback control-loop (FCL) circuitry to generate a delay-compensated output signal responsively to an input reference signal. The FCL circuitry includes a main feedback path, a first subtractor, a delay-compensation feedback path, and a second subtractor. The main feedback path is to generate a main feedback signal responsively to the delay-compensated output signal. The first subtractor is to generate a non-compensated output signal responsively to a difference between the main feedback signal and the input reference signal. The delay-compensation feedback path is to generate a delay-compensation feedback signal responsively to the delay-compensated output signal. The second subtractor is to generate the delay-compensated output signal responsively to a difference between the non-compensated output signal and the delay-compensation feedback signal.

Systems and methods are provided for increasing efficiency of excess loop delay compensation in delta-sigma analog-to-digital converters. In some examples, systems and methods are provided for reducing total capacitance in an embedded excess loop delay compensation digital-to-analog converter (DAC) in a quantizer for a continuous time delta-sigma ADC. In other examples, the excess loop delay compensation DAC can be a current domain DAC, a charge domain DAC, or a voltage domain DAC. Additionally, methods are provided for digitally controlling the gain of an excess loop delay DAC. Furthermore, methods are provided to calibrate a gain mismatch between a main successive approximation register DAC and an excess loop delay DAC. The systems and methods provided herein improve performance of continuous time delta-sigma ADCs. Continuous time delta-sigma ADCs are high precision and power efficient ADCs, often used in audio playback devices and medical devices.

The present disclosure relates generally to techniques for linearizing a digital-to-analog converter (DAC) in a continuous-time sigma-delta ADC. A sigma-delta ADC may be configured with a multibit quantizer for various applications. These applications may require wide-bandwidth high-resolution high-linearity power-efficient ADCs. In some embodiments, a mismatch of a multibit DAC might result in a bottleneck for achieving high linearity performance. Some linearization techniques may achieve high linearity performance. However, for a high-speed sigma-delta ADC, the DAC is configured to be part of a feedback loop. Existing linearization techniques often increase the delay in the feedback loop, which is not desired. Various aspects of the present disclosure provide improvement to linearization techniques by changing the references of the multibit quantizer. As a result, this reduces delay in the feedback loop of the sigma-delta modulator, which is beneficial for high-speed sigma-delta ADCs.

The present disclosure relates generally to techniques for linearizing a digital-to-analog converter (DAC) in a continuous-time sigma-delta ADC. A sigma-delta ADC may be configured with a multibit quantizer for various applications. These applications may require wide-bandwidth high-resolution high-linearity power-efficient ADCs. In some embodiments, a mismatch of a multibit DAC might result in a bottleneck for achieving high linearity performance. Some linearization techniques may achieve high linearity performance. However, for a high-speed sigma-delta ADC, the DAC is configured to be part of a feedback loop. Existing linearization techniques often increase the delay in the feedback loop, which is not desired. Various aspects of the present disclosure provide improvement to linearization techniques by changing the references of the multibit quantizer. As a result, this reduces delay in the feedback loop of the sigma-delta modulator, which is beneficial for high-speed sigma-delta ADCs.

A quad signal generator circuit generates four 2.sup.N-1 bit control signals in response to a 2.sup.N-1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2.sup.N-1 unit DAC elements, with each unit DAC element including four switching circuits controlled by corresponding bits of the four 2.sup.N-1 bit control signals. Outputs of the 2.sup.N-1 unit DAC elements are summed to generate an analog output signal. The quad signal generator circuit controls a time delay applied to clock signals relative to the 2.sup.N-1 bit thermometer coded signal and a time delay applied to the 2.sup.N-1 bit thermometer coded signal relative to the delayed clock signals in logically generating the four 2.sup.N-1 bit control signals. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2.sup.N-1 bit thermometer coded signal.

The present disclosure relates generally to techniques for continuous-time sigma-delta analog-to-digital converter (ADC). The continuous-time sigma-delta ADC may include a feed-forward capacitor in parallel with a current-steering excess loop delay (ELD) digital-to-analog converter (DAC), and by creating a zero in a transfer function of a Gm cell, both an ELD feedback loop settling and a main feedback loop may be recovered. As a result, the performance and stability of the continuous-time sigma-delta ADC can be achieved. Additionally, a summation node in the continuous-time sigma-delta ADC may offer flexibility in the architecture design of the continuous-time sigma-delta ADC.

A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.