A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.

An A/D conversion device, which operates in one mode including at least one of a mode, a cyclic mode, and a hybrid mode, includes: a first block that processes an analog input signal by a first amplifier; a second block including a second amplifier; a quantization unit that quantizes one of outputs of the first and second blocks; and a control circuit that switches the mode to perform a control corresponding to the mode.

A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.

Circuits and methods for converting digital input signals into the analog domain are described. Such circuits may perform the conversion in a segmented fashion. For example, a circuit may include a most significant bit (MSB) path and a least significant bit (LSB) path. The MSB path may include a first delta-sigma modulator having first and second outputs and a first digital-to-analog converter coupled to the first output of the first delta-sigma modulator. The LSB path comprises a second delta-sigma modulator comprising a loop filter and a quantizer. The quantizer may have an input coupled to the loop filter and to the digital filter. The LSB path may further include a second digital-to-analog converter coupled to an output of the quantizer. The circuit may further include a digital filter and/or a gain stage interposed between the MSB path and the LSB path.

A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.

Switching circuits controllable to force an input into a circuit and to sense a responsively produced output in multiple ways to produce different combinations of positive and negative polarities of a desired signal and of sources of offsets and 1/f noise. The switching circuits are controlled in a non-ordered time sequence of different combinations of positive and negative polarities of the sources of the offsets and 1/f noise that spreads their energy to a frequency range above the desired signal frequency band. The non-ordered time sequence leaves the polarity of the desired signal unchanged. Uncorrelated delta-sigma modulators may generate the control signal. A DSP processes a resulting spectrum of a digital domain version of the sensed output to measure residual offsets and 1/f noise and adds to an input present at the DSMs a signal equal in magnitude and opposite in sign to the measured residual offsets and 1/f noise.

A partitioned delta-sigma modulator for high-speed applications includes a plurality of modulation stages arranged in parallel to input and output terminals of the modulator and interconnected to one another in series. In some aspects, each of the plurality of modulation stages is configured to combine a first error signal from a prior modulation stage of the plurality of modulation stages with a first digital signal to produce an adder signal. In some aspects, the first error signal includes a delay from the prior modulation stage. Each of the plurality of modulation stages is also configured to convert the adder signal having a first bit width into a quantized signal having a second bit width smaller than the first bit width. Each of the modulation stages is also configured to provide a second error signal based on the quantized signal to a subsequent modulation stage of the plurality of modulation stages.

A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.

An apparatus for a signal processor for Wide-Band Applications is provided. The signal processor includes a plurality of parallel branches. Each parallel branch includes a frequency shifter, a sigma-delta-modulator, and a filter. The output signal of each branch is combined via a signal recombiner. The signal processor is suitable for wide-band applications due to centering the zeros of the sigma-delta-modulator's noise transfer function and filter's noise transfer function at the frequency of the frequency shifter in the same branch of the signal processor. Centering these zeros at the frequency of the frequency shifter shapes the quantization noise added by the sigma-delta-modulator away from the input signal frequency to make it easier to remove the quantization noise. This wideband performance is also achieved due to the design of the embodiment's filters. The embodiments of this invention use filters with symmetric transition bands and a pass-band that is wide enough for use in wireless applications.

A modulator of an analog to digital converter includes a quantizer component configured to generate a digital signal based on a clock input operating at a sample rate. The modulator further includes a first digital to analog converter (DAC) configured to generate first DAC output at half the sample rate. The modulator further includes a second DAC configured to generate second DAC output at half the sample rate, where the first DAC and the second DAC are updated at alternate cycles of the clock input.