A ramp generator providing ramp signal with high resolution fine gain includes a current mirror having a first and second paths to conduct a capacitor current and an integrator current responsive to the capacitor current. First and second switched capacitor circuits are coupled to the first path. A fractional divider circuit is coupled to receive a clock signal to generate in response to an adjustable fractional divider ratio K a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits. The first and second switched capacitor circuits are coupled to be alternatingly charged by the capacitor current and discharged in response to each the switched capacitor control signal. An integrator coupled is to the second path to generate the ramp signal in response to the integrator current.

Systems and methods for correction of sigma-delta analog-to-digital converters (ADCs) using neural networks are described. In an illustrative, non-limiting embodiment, a device may include: an ADC; a filter coupled to the ADC, where the filter is configured to receive an output from the ADC and to produce a filtered output; and a neural network coupled to the filter, where the neural network is configured to receive the filtered output and to produce a corrected output.

An incremental analog-to-digital converter including a first-stage non-delay memorization element and other elements is disclosed. An ending time point of a second reset signal received by the first-stage non-delay memorization element is later than an ending time point of a first reset signal received by the other elements by at least one clock cycle, a reset duration of the first-stage non-delay memorization element is longer than a reset duration of the other element, so that the first-stage non-delay memorization element can be prevented from occurring overshoot or spike on an output thereof, and the incremental analog-to-digital converter can maintain a good signal-to-noise and distortion ratio under the condition that the internal elements has low swing limits.

An incremental analog-to-digital converter including a first-stage non-delay memorization element and other elements is disclosed. An ending time point of a second reset signal received by the first-stage non-delay memorization element is later than an ending time point of a first reset signal received by the other elements by at least one clock cycle, a reset duration of the first-stage non-delay memorization element is longer than a reset duration of the other element, so that the first-stage non-delay memorization element can be prevented from occurring overshoot or spike on an output thereof, and the incremental analog-to-digital converter can maintain a good signal-to-noise and distortion ratio under the condition that the internal elements has low swing limits.

A circuitry for an incremental delta-sigma modulator includes at least an incremental delta-sigma modulator and a sample-and-hold element, the sample-and-hold element being arranged in front of the incremental delta-sigma modulator and providing an input voltage for the incremental delta-sigma modulator in the charged state, wherein the sample-and-hold element includes a capacitor for charging the input voltage for the incremental delta-sigma modulator, wherein a first switch is arranged in front of the capacitor, and a second switch is arranged behind the capacitor, wherein the first switch is open when the second switch is closed so as to provide, at the incremental delta-sigma modulator, an input voltage decreasing in amount, in particular a decaying input voltage, or wherein the second switch is open when the first switch is closed so as to charge the capacitor of the sample-and-hold element. In addition, a method of operating a circuitry for an incremental delta-sigma modulator is proposed.

An analog circuit including a voltage regulator, at least one analog-to-digital convertor (ADC), at least one comparator and a multiplexer is provided. The voltage regulator generates an output voltage. The at least one ADC generates at least one digital signal. The multiplexer is configured to conduct the at least one comparator to either the voltage regulator or the at least one ADC. When the voltage regulator is triggered, the multiplexer conducts the at least one comparator to the voltage regulator, and the voltage regulator generates the output voltage according to an output of the at least one comparator. When the at least one ADC is triggered, the multiplexer conducts the at least one comparator to the at least one ADC, and the at least one ADC generates the at least one digital signal according to the output of the at least one comparator.

Provided is an AD converter, including: an analog signal input circuit, configured to be input with an analog input signal, and output a first analog output signal based on the analog input signal and a second analog output signal based on the analog input signal at different timing; an integral circuit, configured to integrate the first analog output signal and the second analog output signal and output the first integral signal and the second integral signal; a predictive circuit, configured to predict an integral signal output after the output by the integral circuit based on the first integral signal and the second integral signal output by the integral circuit, and output a predictive integral signal; and a quantization circuit, configured to generate a digital signal with the predictive integral signal quantized.

A system and method of replicating and cancelling chopping folding error in delta-sigma modulators. The modulator may include a loop filter coupled to a quantizer providing a digital signal, chopper circuitry that chops analog signals of the loop filter at a chopping frequency, and chopping folding error cancellation circuitry that replicates and cancels a chopping folding error of the chopper circuitry to provide a corrected digital signal. A digital chopper or multiplier chops the digital signal to provide a chopped digital signal, and the chopped digital signal is either amplified or multiplied by a gain value or digitally filtered to replicate the chopping folding error, which is then subtracted from the digital signal for correction. The timing and duty cycle of the chopping frequency may be adjusted. Timing and duty cycle adjustment may be calibrated along with the filtering.

An analogue to digital converter for converting the analogue output of a dual conversion gain pixel of an image sensor. The dual conversion gain pixel is operable to sequentially output a reset pixel value and a signal pixel value sequentially with both a first gain and a second gain different to the first gain. An image sensor comprising the analogue to digital converter, a system comprising the image sensor and a method are also described herein.

Provided is a delta-sigma modulator including a first integral unit configured to integrate an input analog signal, a second integral unit configured to integrate a signal output by the first integral unit, a quantizer configured to quantize a signal output by the second integral unit, a DA converter configured to perform DA conversion on an output of the quantizer and output a feedback signal to be fed back to the first integral unit, and a control unit configured to perform control to cause the first integral unit and the second integral unit to perform different integral operations during a first period and a second period, in which the second integral unit is configured to receive the feedback signal output by the DA converter via the first integral unit and integrate the feedback signal during the first period and the second period.