An analog-to-digital conversion apparatus is provided. The analog-to-digital conversion apparatus includes an integrated circuit (IC) configured to generate a first interrupt request; and an analog-to-digital converter included in an integrated circuit, wherein the analog-to-digital converter is configured to receive a plurality of analog values from a plurality of channels, and convert at least a portion of the received analog values that correspond to at least a portion of channels of the plurality of channels, that are selected based on the first interrupt request into at least a portion of digital values.

An analog-to-digital converting device includes: a main analog-to-digital converter configured to convert an analog signal output from a sensor to a digital signal; and a monitoring unit configured to monitor the digital signal converted by the main analog-to-digital converter. The main analog-to-digital converter is provided by a special purpose IC arranged separately from a microcomputer for controlling the main analog-to-digital converter. The monitoring unit includes multiple sub analog-to-digital converters each of which having a conversion accuracy lower than that of the main analog-to-digital converter and converting the analog signal output from the sensor to a digital signal. The monitoring unit sets a predetermined threshold based on conversion values of the digital signals converted by the multiple sub analog-to-digital converters, and compares a conversion value of the digital signal converted by the main analog-to-digital converter with the predetermined threshold.

A delta-sigma modulator may include a loop filter, a quantizer, an input gain element having a programmable input gain and coupled between an input of the delta-sigma modulator and an input of the loop filter, a feedforward gain element having a programmable feedforward gain and coupled between the input of the delta-sigma modulator and an output of the loop filter, and a quantizer gain element having a quantizer gain and coupled between the output of the loop filter and an input of the quantizer. The programmable input gain is controlled in order to control a variable gain of the delta-sigma modulator. The programmable feedforward gain is controlled to be equal to the ratio of the programmable input gain and the quantizer gain such that the delta-sigma modulator has a fixed phase response.

Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal. Hereby, the digital inputs provided to the DACs are non-randomized.

An exemplary incremental two-step capacitance-to-digital converter (CDC) with a time-domain sigma-delta modulator (TDΔΣM) includes a voltage-controlled oscillator (VCO)-based integrator that can be used in a low-order loop configuration. Example prototypes are disclosed, which when fabricated in 40-nm CMOS technology, provides CDC resolution of 0.29 fF while dissipating only 0.083 nJ per conversion.

A channel driver circuit includes a differential module and a driver module. In some examples, the channel driver circuit also includes a sigma-delta module. The differential module receives, via a single node of a load, a channel driving signal that is provided to the load at the single node (e.g., that is based on an electrical characteristic of the load) and generates an analog error signal that is based on the channel driving signal and a reference signal. The driver module is coupled to the differential module and generates the channel driving signal based on the analog error signal or a digital error signal corresponding to the analog error signal and transmits the channel driving signal via the single node to the load. The channel driver circuit simultaneously transmits the channel driving signal to the load at the single node and senses the channel driving signal at the single node.

A variety of methods, controllers and electric machine systems are described that facilitate pulsed control of electric machines (e.g., electric motors and generators) to improve the machine's energy conversion efficiency. Under selected operating conditions, the electric machine is intermittently driven (pulsed). The pulsed operation causes the output of the electric machine to alternate between a first output level and a second output level that is lower than the first output level. The output levels are selected such that at least one of the electric machine and a system that includes the electric machine has a higher energy conversion efficiency during the pulsed operation than the electric machine would have when operated at a third output level that would be required to drive the electric machine in a continuous manner to deliver the desired output. In some embodiments, the second output level is zero torque.

The digital-output temperature sensor includes a temperature sensor circuit, a current mirror circuit which makes a mirror current of a temperature detection current flow and pulls in a mirror current of a reference current to thereby output a first difference current from a first output node and output a second difference current from a second output node, a chopping circuit, and an A/D conversion circuit. The chopping circuit performs a chopping operation of making the mirror current of the reference current flow in a second state through a transistor of the current mirror circuit through which the mirror current of the temperature detection current flows in a first state, and making the mirror current of the temperature detection current flow in the second state through the transistor of the current mirror circuit through which the mirror current of the reference current flows in the first state.

A quantizer for a sigma-delta modulator, a sigma-delta modulator, and a method of shaping noise are provided. The quantizer includes: an integrator configured to generate, in a K.sup.th sampling period, a quantization error signal for a K.sup.th period according to an internal signal, a quantization error signal for a (K−1).sup.th period, a filtered quantization error signal for the (K−1).sup.th period and a filtered quantization error signal for a (K−2).sup.th period; an integrating capacitor configured to store the quantization error signal for the K.sup.th period, to weight the internal signal in a (K+1).sup.th sampling period; a passive low-pass filter configured to acquire the quantization error signal for the K.sup.th period in a K.sup.th discharge period, and feed back the filtered quantization error signal to the integrator in a (K+1).sup.th sampling period and a (K+2).sup.th sampling period; and a comparator configured to quantize the quantization error signal for the K.sup.th period.

Analog to digital conversion circuitry has an input sampling buffer, which has an input sampling capacitor for sampling an analog signal. The conversion circuitry also has a successive-approximation-register analog to digital converter (SAR-ADC) which converts the sampled analog signal to a digital signal. The input sampling buffer has an amplifier and a gain-control capacitor, and has an amplification configuration and an error-feedback configuration. In the amplification configuration, the input sampling capacitor is coupled to the amplifier and gain-control capacitor, with the gain-control capacitor connected in feedback with the amplifier, for applying gain to the sampled analog signal. In the error-feedback configuration, the gain-control capacitor is decoupled from the input sampling capacitor and receives a residue voltage from the SAR-ADC, such that the level of the analog signal determined in the amplification configuration varies depending on the residue voltage received onto the gain-control capacitor in the error-feedback configuration.