A method and system for controlling electrical devices, such as lights capable of emitting different colours or colour sequences (shows). A multi-field command protocol is proposed to transmit command messages from a line controller to a controllable electrical device (light) to control its mode of operation, and optionally at least one dimension associated with the mode (e.g. light colour, and brightness and/or colour saturation, or blending colour show and speed of changing colours). The protocol comprises brief interruptions to the power supplied to the electrical device comprising a first variable length OFF time, a variable length ON time following the first OFF time, and a second variable length OFF time following the ON time. Together these times form three information fields having values represented by their respective lengths/durations. The fields define a selected mode of operation of the electrical device, and optionally at least one dimension associated with the mode.

A method for transmitting information using a pulse may comprise transmitting, via a channel between a first device and a second device, an idle state for an idle time; and transmitting, via the channel, a pulse state for a pulse time, wherein the idle time and the pulse time define a value for a data word being transmitted, and wherein the duration of one or more of the idle time and the pulse time vary depending upon the value of the data word.

A method for transmitting information using a pulse may comprise transmitting, via a channel between a first device and a second device, an idle state for an idle time; and transmitting, via the channel, a pulse state for a pulse time, wherein the idle time and the pulse time define a value for a data word being transmitted, and wherein the duration of one or more of the idle time and the pulse time vary depending upon the value of the data word.

A single-bit audio stream can be converted to a modified single-bit audio stream with a constant edge rate while maintaining a modulation index of the original audio stream using direct mapping. With direct mapping, a pre-filter bank may be combined with a multi-bit symbol mapper to select symbols for the modified audio stream with a constant edge rate per symbol and the same modulation index as the original audio stream. The output of the pre-filter bank may be an audio stream with no consecutive full-scale symbols. Using the output of the pre-filter bank, a multi-bit symbol mapper may use the symbol selector to output a symbol with a constant edge rate per symbol and the same modulation index as the original signal. The symbols may be converted to an analog signal for reproduction of audio content using a transducer.

A single-bit audio stream can be converted to a modified single-bit audio stream with a constant edge rate while maintaining a modulation index of the original audio stream using direct mapping. With direct mapping, a pre-filter bank may be combined with a multi-bit symbol mapper to select symbols for the modified audio stream with a constant edge rate per symbol and the same modulation index as the original audio stream. The output of the pre-filter bank may be an audio stream with no consecutive full-scale symbols. Using the output of the pre-filter bank, a multi-bit symbol mapper may use the symbol selector to output a symbol with a constant edge rate per symbol and the same modulation index as the original signal. The symbols may be converted to an analog signal for reproduction of audio content using a transducer.

The present invention provides a receiver including a sampling circuit, a data sampling point selection circuit and a determination circuit. The sampling circuit is configured to use a clock signal to sample an input signal to generate a sampled signal, wherein a frequency of the clock signal is greater than a frequency of the input signal. The data sampling point selection circuit is configured to filter start point data to generate a filtered start point data, and to generate a data sampling point by adding an offset to the filtered start point data, wherein the start point data corresponds to a time point that a sampled value of sampled signal starts to change. The determination circuit is configured to refer to a sampled value corresponding to the data sampling point in the sampled signal to determine a logical value of a digital output signal corresponding to the input signal.

The present invention provides a receiver including a sampling circuit, a data sampling point selection circuit and a determination circuit. The sampling circuit is configured to use a clock signal to sample an input signal to generate a sampled signal, wherein a frequency of the clock signal is greater than a frequency of the input signal. The data sampling point selection circuit is configured to filter start point data to generate a filtered start point data, and to generate a data sampling point by adding an offset to the filtered start point data, wherein the start point data corresponds to a time point that a sampled value of sampled signal starts to change. The determination circuit is configured to refer to a sampled value corresponding to the data sampling point in the sampled signal to determine a logical value of a digital output signal corresponding to the input signal.

The present invention provides a receiver including a sampling circuit, a data sampling point selection circuit and a determination circuit. The sampling circuit is configured to use a clock signal to sample an input signal to generate a sampled signal, wherein a frequency of the clock signal is greater than a frequency of the input signal. The data sampling point selection circuit is configured to filter start point data to generate a filtered start point data, and to generate a data sampling point by adding an offset to the filtered start point data, wherein the start point data corresponds to a time point that a sampled value of sampled signal starts to change. The determination circuit is configured to refer to a sampled value corresponding to the data sampling point in the sampled signal to determine a logical value of a digital output signal corresponding to the input signal.

Systems, apparatuses, and methods for implementing an anti-aliasing technique for a time-to-digital converter are described. A pulse generator generates a pulse with a width that is representative of a voltage level of a supply voltage. A buffer chain receives the pulse from the pulse generator. A first sum is calculated by adding together a number of one bits in a first portion of the buffer chain. Also, a second sum is calculated by adding together a number of one bits in a second portion of the buffer chain. Then, a third sum is calculated by adding the first sum to the second sum if the first sum is saturated. Otherwise, the third sum is equal to the first sum if the first sum is not saturated. The third sum is used as a representation of the voltage level of the supply voltage.

The present technology relates to a signal processing device, a signal processing method, and a program that make it possible to suppress deterioration in audio characteristics. The signal processing device includes: a low-pass filter that performs filter processing on a PDM signal; and a PWM conversion unit that performs PWM conversion on a multibit signal obtained by the filter processing and generates a PWM signal. The present technology can be applied to an audio reproduction system.