Methods, systems, and apparatus, including computer-readable storage media for hardware compression and decompression. A system can include a decompressor device coupled to a memory device and a processor. The decompressor device can be configured to receive, from the memory device, compressed data that has been compressed using an entropy encoding, process the compressed data using the entropy encoding to generate uncompressed data, and send the uncompressed data to the processor. The system can also include a compressor device configured to generate, from uncompressed data, a probability distribution of codewords, generate a code table from the probability distribution, and compress incoming data using the generated code table.

Methods, systems, and apparatus, including computer-readable storage media for hardware compression and decompression. A system can include a decompressor device coupled to a memory device and a processor. The decompressor device can be configured to receive, from the memory device, compressed data that has been compressed using an entropy encoding, process the compressed data using the entropy encoding to generate uncompressed data, and send the uncompressed data to the processor. The system can also include a compressor device configured to generate, from uncompressed data, a probability distribution of codewords, generate a code table from the probability distribution, and compress incoming data using the generated code table.

Methods, systems, and apparatus, including computer-readable storage media for hardware compression and decompression. A system can include a decompressor device coupled to a memory device and a processor. The decompressor device can be configured to receive, from the memory device, compressed data that has been compressed using an entropy encoding, process the compressed data using the entropy encoding to generate uncompressed data, and send the uncompressed data to the processor. The system can also include a compressor device configured to generate, from uncompressed data, a probability distribution of codewords, generate a code table from the probability distribution, and compress incoming data using the generated code table.

A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.

A physical layer circuit at a transmitter includes an encoding chain and a plurality of flip-flops. The encoding chain, including encoding units coupled in series, is configured to encode a plurality of symbols to generate a plurality of first wire states. The encoding units are arranged to receive the symbols respectively, and convert respective symbol values of the symbols to the first wire states respectively. A first encoding unit is configured to convert a symbol value of a corresponding symbol according to a second wire state provided by a second encoding unit. The flip-flops are arranged to receive and output the first wire states according to a clock signal, respectively. One of the flip-flops is coupled between the first encoding unit and the second encoding unit. The second wire state provided by the second encoding unit is sent to the first encoding unit through the one of the flip-flops.

In certain aspects, a circuit for modulo-3 operation has an encoder stage coupled to a binary number, wherein the encoder stage includes one or more encoders, each one of the one or more encoders receives one or two binary bits of the binary number and generates a unary code of encoder. The circuit for modulo-3 operation further has one or more levels of reduction stage, wherein a first level of the one or more levels of reduction stage includes one or more mergers of first reduction, each one of the one or more mergers of first reduction receives two unary codes of encoder or a unary code of encoder and a bit from the binary number and generates a unary code of first reduction.

A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.

A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.

A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.

A physical layer circuit at a transmitter includes an encoding chain and a plurality of flip-flops. The encoding chain, including encoding units coupled in series, is configured to encode a plurality of symbols to generate a plurality of first wire states. The encoding units are arranged to receive the symbols respectively, and convert respective symbol values of the symbols to the first wire states respectively. A first encoding unit is configured to convert a symbol value of a corresponding symbol according to a second wire state provided by a second encoding unit. The flip-flops are arranged to receive and output the first wire states according to a clock signal, respectively. One of the flip-flops is coupled between the first encoding unit and the second encoding unit. The second wire state provided by the second encoding unit is sent to the first encoding unit through the one of the flip-flops.