A communication system includes: a transmitter including: an arithmetic decoder configured to generate an output symbol based on input bits and a symbol frequency table that sets frequencies of excluded symbols to 0 and frequencies of allowed symbols to non-zero values, the transmitter being configured to iteratively generate a sequence of restricted packets and an ending state, the sequence of restricted packets excluding instances of the one or more excluded symbols and to transmit the sequence of restricted packets and the ending state on a channel; and a receiver including: an arithmetic encoder configured to compute an output state based on an input state, an input symbol, and the symbol frequency table, the receiver being configured to: supply an ending state received from the channel and the restricted packets to the arithmetic encoder to iteratively generate a final state, and recover a bit sequence from the final state.

The technology relates to an encoding device, an encoding method, a decoding device, a decoding method, and a program enabling encoding with favorable transmission efficiency with a controlled running disparity.

A calculation section divides inputted data into N or M bits to calculate a first running disparity of an N or M bit data string. A determination section determines whether the data string is inverted based on the first running disparity calculated by the calculation section and a second running disparity calculated therebefore. An addition section inverts or non-inverts the data string based on a determination result by the determination section to add a flag indicating the determination result for outputting. The determination section determines not to perform inversion when the data string is a control code. The addition section adds the flag assigned to the control code. The technology is applicable to a device communicating in an SLVS-EC specification.

Systems, apparatuses, and methods related to bit string conversion are described. A memory resource and/or logic circuitry may be used in performance of bit string conversion operations. The logic circuitry can perform operations on bit strings, such as universal number and/or posit bit strings, to alter a level of precision (e.g., a dynamic range, resolution, etc.) of the bit strings. For instance, the memory resource can receive data comprising a bit string having a first quantity of bits that correspond to a first level of precision. The logic circuitry can determine that the bit string having the first quantity of bits has a particular data pattern and alter the first quantity of bits to a second quantity of bits that correspond to a second level of precision based, at least in part, on the determination that the bit string has the particular data pattern.

Systems, apparatuses, and methods related to bit string conversion are described. A memory resource and/or logic circuitry may be used in performance of bit string conversion operations. The logic circuitry can perform operations on bit strings, such as universal number and/or posit bit strings, to alter a level of precision (e.g., a dynamic range, resolution, etc.) of the bit strings. For instance, the memory resource can receive data comprising a bit string having a first quantity of bits that correspond to a first level of precision. The logic circuitry can determine that the bit string having the first quantity of bits has a particular data pattern and alter the first quantity of bits to a second quantity of bits that correspond to a second level of precision based, at least in part, on the determination that the bit string has the particular data pattern.

An aspect of the present invention is a communication system including: an encoding unit configured to transform an input symbol sequence into an output symbol sequence, the input symbol sequence being a sequence of first symbols, the output symbol sequence being a sequence of second symbols; and a decoding unit configured to transform the output symbol sequence into the input symbol sequence in accordance with a decoding-side transformation mapping for transforming the output symbol sequence into the input symbol sequence that is a transformation source for the output symbol sequence, wherein the encoding unit transforms the input symbol sequence into the output symbol sequence in accordance with encoding-side transformation destination candidate information, the input symbol sequence, and a transformation probability, the encoding-side transformation destination candidate information being information indicating candidates of a transformation destination for the input symbol sequence, the transformation probability being a probability of transformation into the transformation destination indicated by the encoding-side transformation destination candidate information, and a probability of appearance of the second symbol conforms to a predefined prescribed probability distribution.

A method and structure for probabilistic shaping and compensation techniques in coherent optical receivers. According to an example, the present invention provides a method and structure for an implementation of distribution matcher encoders and decoders for probabilistic shaping applications. The techniques involved avoid the traditional implementations based on arithmetic coding, which requires intensive multiplication functions. Furthermore, these probabilistic shaping techniques can be used in combination with LDPC codes through reverse concatenation techniques.

Circuits, methods, and apparatus for efficiently implementing encoding and decoding between binary and multilevel data.

A method and an assemblage for post-processing an output of a random source of a random generator are presented. In the method, an output signal of the random source is compressed, thereby yielding a sequence of compressed signal values that are checked in terms of their distribution.

A method and an assemblage for post-processing an output of a random source of a random generator are presented. In the method, an output signal of the random source is compressed, thereby yielding a sequence of compressed signal values that are checked in terms of their distribution.

A method compares text strings having Unicode encoding. The method receives a first string S=s.sub.1s.sub.2 . . . s.sub.n and a second string T=t.sub.1t.sub.2 . . . t.sub.m, where s.sub.1, s.sub.2, . . . , s.sub.n and t.sub.1, t.sub.2, . . . , t.sub.m are Unicode characters. The method computes a first string weight for the first string S according to a weight function ƒ. When S consists of ASCII characters, ƒ(S)=S. when S includes one or more non-replaceable non-ASCII characters, the first string weight ƒ(S) is a concatenation of an ASCII weight prefix ƒ.sub.A(S) and a Unicode weight suffix ƒ.sub.U(S). The method also computes a second string weight for the second text string T. Equality of the strings is tested using the string weights.