H03M7/26

Lossless exponent and lossy mantissa weight compression for training deep neural networks

Systems, methods, and apparatuses are provided for compressing values. A plurality of parameters may be obtained from a memory, each parameter comprising a floating-point number that is used in a relationship between artificial neurons or nodes in a model. A mantissa value and an exponent value may be extracted from each floating-point number to generate a set of mantissa values and a set of exponent values. The set of mantissa values may be compressed to generate a mantissa lookup table (LUT) and a plurality of mantissa LUT index values. The set of exponent values may be encoded to generate an exponent LUT and a plurality of exponent LUT index values. The mantissa LUT, mantissa LUT index values, exponent LUT, and exponent LUT index values may be provided to one or more processing entities to train the model.

Method and apparatus for efficient multiplication to improve performance in computational machines

A method and apparatus is disclosed for determining a stochastic binary string (SBS) representing a value based on the value represented in binary two's complement. Several different generators are disclosed for generating SBS strings, each being generated to have particular features that are advantageous under various conditions in which the string is to be multiplied with another SBS string. Several such generators can be presented and selected depending upon the particular values to be converted to SBS representation and the functions to be performed on those values.

Method and apparatus for efficient multiplication to improve performance in computational machines

A method and apparatus is disclosed for determining a stochastic binary string (SBS) representing a value based on the value represented in binary two's complement. Several different generators are disclosed for generating SBS strings, each being generated to have particular features that are advantageous under various conditions in which the string is to be multiplied with another SBS string. Several such generators can be presented and selected depending upon the particular values to be converted to SBS representation and the functions to be performed on those values.

STOCHASTIC COMPUTATION USING DETERMINISTIC BIT STREAMS
20170359082 · 2017-12-14 ·

In some examples, a device includes an integrated circuit comprising a computational unit configured to process at least two input bit streams that each include a sequential set of data bits or two or more sets of data bits in parallel that is deterministically encoded to represent numerical values based on a probability that any data bit in the bit stream is high. In some examples, the computational unit includes a convolver configured to generate pair-wise bit combinations of the data bits of the input bit streams. In some examples, e computational unit further includes a stochastic computational unit configured to perform a computational operation on the pair-wise bit combinations and produce an output bit stream having a set of data bits indicating a result of the computational operation based on a probability that any data bit in the set of data bits of the output bit stream is high.

STOCHASTIC COMPUTATION USING DETERMINISTIC BIT STREAMS
20170359082 · 2017-12-14 ·

In some examples, a device includes an integrated circuit comprising a computational unit configured to process at least two input bit streams that each include a sequential set of data bits or two or more sets of data bits in parallel that is deterministically encoded to represent numerical values based on a probability that any data bit in the bit stream is high. In some examples, the computational unit includes a convolver configured to generate pair-wise bit combinations of the data bits of the input bit streams. In some examples, e computational unit further includes a stochastic computational unit configured to perform a computational operation on the pair-wise bit combinations and produce an output bit stream having a set of data bits indicating a result of the computational operation based on a probability that any data bit in the set of data bits of the output bit stream is high.

Low-discrepancy deterministic bit-stream processing using Sobol sequences

Example devices are described that include a computational unit configured to process first set of data bits encoding a first numerical value and a second set of data bits encoding a second numerical value. The computational unit includes a bit-stream generator configured to generate bit combinations representing first and second bit sequences that encode the first and second numerical values, respectively, based on a proportion of the data bits in the sequence that are high relative to the total data bits. The first bit sequence is generated using a first Sobol sequence source, and the second bit sequence is generated using a second Sobol sequence source different from the first Sobol sequence source. The device also includes computation logic configured to perform a computational operation on the bit combinations and produce an output bit-stream having a set of data bits indicating a result of the computational operation.

Low-discrepancy deterministic bit-stream processing using Sobol sequences

Example devices are described that include a computational unit configured to process first set of data bits encoding a first numerical value and a second set of data bits encoding a second numerical value. The computational unit includes a bit-stream generator configured to generate bit combinations representing first and second bit sequences that encode the first and second numerical values, respectively, based on a proportion of the data bits in the sequence that are high relative to the total data bits. The first bit sequence is generated using a first Sobol sequence source, and the second bit sequence is generated using a second Sobol sequence source different from the first Sobol sequence source. The device also includes computation logic configured to perform a computational operation on the bit combinations and produce an output bit-stream having a set of data bits indicating a result of the computational operation.

Device for generating a random electrical signal and associated architecture

A device for generating a random electric signal, including an input duct, an output duct, a generator of magnetic particles generating magnetic particles in the input duct, a diffusion chamber connected to the input duct and the output duct, wherein the diffusion chamber is designed to diffuse the generated magnetic particles, a displacement unit for displacement of the generated magnetic particles towards the diffusion chamber, and a converter that is designed to generate an electrical signal proportional to a characteristic, wherein the characteristic is the particle density in the diffusion chamber or the passage of magnetic particles at a predetermined location of an output duct connected to the diffusion chamber.

Device for generating a random electrical signal and associated architecture

A device for generating a random electric signal, including an input duct, an output duct, a generator of magnetic particles generating magnetic particles in the input duct, a diffusion chamber connected to the input duct and the output duct, wherein the diffusion chamber is designed to diffuse the generated magnetic particles, a displacement unit for displacement of the generated magnetic particles towards the diffusion chamber, and a converter that is designed to generate an electrical signal proportional to a characteristic, wherein the characteristic is the particle density in the diffusion chamber or the passage of magnetic particles at a predetermined location of an output duct connected to the diffusion chamber.

Parallel computing using stochastic circuits and deterministic shuffling networks

In some examples, a device includes shuffling circuitry configured to receive an input unary bit stream and generate a shuffled bit stream by selecting n-tuple combinations of bits of the input unary bit stream. The device also includes stochastic logic circuitry having a plurality of stochastic computational units configured to perform operations on the shuffled bit stream in parallel to produce an output unary bit stream, each of the stochastic computational units operating on a different one of the n-tuple combinations of the bits.