A quantizer and a method for a sigma-delta modulator circuit that may be used as a component within an adaptive-noise cancelling headphone are presented. An apparatus includes a quantizer to receive an input signal with successive input values and quantizes the input signal at discrete intervals. This is done by mapping the input value of the input signal at each interval to one of a plurality of quantization levels with three or more quantization levels that are non-uniformly spaced. The plurality of quantization levels has a first portion with two or more quantization levels having the same sign and being proportional to a first fraction having one as its numerator and two to a power of a first variable as its denominator, the first variable being an integer and having a different value for each of the two or more quantization levels of the first portion.

Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers and MACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications.

According to one or more embodiments, a network node for communicating with at least one radio unit is provided. The network node including processing circuitry configured to: determine at least one code frame characteristic of a non-linear grid, map in-phase and quadrature, I/Q, data to non-linear grid having a plurality of regions that correspond to a plurality of code words where a plurality of bit sizes of the plurality of code words is a function of a radial distance from an origin of the non-linear grid, select a subset of the plurality of code words based at least in part on a target data rate for transmission, and cause transmission of the I/Q data based at least in part on the selected subset of the plurality of code words.

There is provided a signal processing device including a signal coincidence detection portion which detects samples, in which values based on a number of times of appearance of bits coincide with each other over a plurality of samples within a pre-set period, between a first modulated signal obtained by delaying an input signal obtained by modulation and a second modulated signal obtained by subjecting the input signal to the modulation again, a signal changeover portion which switches between the first modulated signal and the second modulated signal for outputting, and a switching control portion which controls the switching between the first modulated signal and the second modulated signal by the signal changeover portion in the samples in which the values based on the number of times of the appearance coincide with each other obtained by the signal coincidence detection portion.