A processing device for executing a machine learning neural network operation includes memory and a processor. The processor is configured to receive input data at a layer of the machine learning neural network operation, receive a plurality of sorted filters to be applied to the input data, apply the plurality of sorted filters to the input data to produce a plurality of different feature maps, compress the plurality of different feature maps according to a similarity of the feature maps relative to each other and store the plurality of different feature maps in the memory.

A processing device for executing a machine learning neural network operation includes memory and a processor. The processor is configured to receive input data at a layer of the machine learning neural network operation, receive a plurality of sorted filters to be applied to the input data, apply the plurality of sorted filters to the input data to produce a plurality of different feature maps, compress the plurality of different feature maps according to a similarity of the feature maps relative to each other and store the plurality of different feature maps in the memory.

A radio frequency system. In some embodiments, the system includes a one-bit receiver, and the one-bit receiver includes a digital pseudo random noise generator, a one-bit digital to analog converter, a power combiner, a one-bit analog to digital converter, and a digital subtraction circuit. The digital pseudo random noise generator produces a signal added to the received signal before analog to digital conversion. After analog to digital conversion, a delayed version of the dither is subtracted from the digital signal.

A radio frequency system. In some embodiments, the system includes a one-bit receiver, and the one-bit receiver includes a digital pseudo random noise generator, a one-bit digital to analog converter, a power combiner, a one-bit analog to digital converter, and a digital subtraction circuit. The digital pseudo random noise generator produces a signal added to the received signal before analog to digital conversion. After analog to digital conversion, a delayed version of the dither is subtracted from the digital signal.

A hardware accelerator device is provided with circuitry to perform one or more reversible data transforms on data based on a request and compress the transformed data to generate compressed transformed data. The hardware accelerator device generates an output including the compressed transformed data and transform metadata indicating the set of reversible data transforms applied to the compressed transformed data.

There is provided a signal processing device including a signal coincidence detection portion which detects samples, in which values based on a number of times of appearance of bits coincide with each other over a plurality of samples within a pre-set period, between a first modulated signal obtained by delaying an input signal obtained by modulation and a second modulated signal obtained by subjecting the input signal to the modulation again, a signal changeover portion which switches between the first modulated signal and the second modulated signal for outputting, and a switching control portion which controls the switching between the first modulated signal and the second modulated signal by the signal changeover portion in the samples in which the values based on the number of times of the appearance coincide with each other obtained by the signal coincidence detection portion.