A transmitter supports beamforming function using a plurality of antenna elements. The transmitter includes a dither signal generator which, in operation, generates pseudo random sequence signals as dither signals for lower bits of digital signals, the pseudo random sequence signals being different from each other, the digital signals each corresponding to respective one of the plurality of antenna elements, and a plurality of digital-to-analog converters which, in operation, adds the dither signals generated by the dither signal generator to the lower bits of the digital signals, and converts only upper bits of addition results of the digital signals and the dither signals into analog signals.

An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry. The ADDA RF transceiver includes one of more ADCs, DSPs, and DACs, all on a single ASIC. Further, the circuitry is to be radiation tolerant for high availability and reliability in the ionizing radiation environment present in the space environment.

A programmable drive-sense unit (DSU) includes a drive-sense circuit operably coupled to a load, wherein the drive-sense circuit is configured to drive and simultaneously to sense the load via a single line, and produce an analog output based on the sensing the load. The programmable DSU also includes an analog to digital circuit operably coupled to the drive-sense circuit, where the analog to digital circuit is operable to generate a digital output based on the analog output and in accordance with one or more programmable operational parameters to achieve one or more of load sensing objectives associated with the sensing of the load and data processing objectives associated with the sensing of the load.

A radio frequency (RF) generator incorporates an automatic level control (ALC) circuit to control the output level of the RF signal where the ALC circuit implements synchronized ADC sampling, pulse sample indexing, gated accumulation to enable fast ALC loop control, especially for pulse-modulated RF signals. In other embodiments, the ALC circuit implements multi-level control for multi-level RF signals. In this manner, the RF generator uses the ALC circuit to generate an RF signal having a constant power level for RF signals having any pulse shape or output levels. In other embodiments, a clock generation circuit in an impedance matching network synchronizes a slave clock to a clock signal of the RF signal when the load impedance is resistive only or when the clock signal of the RF signal has a given phase condition.

A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.

Embodiments herein describe an integrated circuit with a digital front end (DFE) that includes multiple hardened mixers that can be configured to support multiple different radio paths. The DFE provides the ability to distribute the processing across the multiple mixers, which can be combined and synchronized to create a larger mixer or may be used in other combinations to create multiple discrete mixers.

A current mode end-to-end signal path includes, a digital to analog converter (DAC), operating in current mode and an upconverting mixer, operating in current mode and operatively coupled to the DAC, wherein analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

An automatic gain control system for a receiver, including: an automatic gain control loop (40) adapted to be coupled to both a first transimpedance amplifier (12) coupled to a first analog-to-digital converter (14) forming a first tributary and a second transimpedance amplifier (12) coupled to a second analog-to-digital converter (14) forming a second tributary; and an offset gain control voltage to gain balance a transimpedance amplifier gain of the first tributary and a transimpedance amplifier gain of the second tributary. The automatic gain control loop can be analog. Also, the automatic gain control loop can be implemented in hardware or firmware.

An apparatus is comprised of a processor, a fast-locking Phase-Locked Loop Waveform Generator (PLLWG), an amplifier circuit, and a voltage controlled oscillator (VCO). The processor generates data program signals to program the PLLWG and generates a trigger command signal instructing the PLLWG to generate an analog tuning signal. The PLLWG, coupled to the processor, generates the analog tuning signal based on the trigger command signal. The amplifier circuit, coupled to the PLLWG, receives the analog tuning signal, amplify the analog tuning signal, and generates a control voltage. The VCO, coupled to the amplifier circuit, receives the control voltage and amplifies the control voltage to generate an amplified Radio Frequency (RF) channel frequency signal.

A radio frequency (RF) generator incorporates an automatic level control (ALC) circuit to control the output level of the RF signal where the ALC circuit implements synchronized ADC sampling, pulse sample indexing, gated accumulation to enable fast ALC loop control, especially for pulse-modulated RF signals. In other embodiments, the ALC circuit implements multi-level control for multi-level RF signals. In this manner, the RF generator uses the ALC circuit to generate an RF signal having a constant power level for RF signals having any pulse shape or output levels. In other embodiments, a clock generation circuit in an impedance matching network synchronizes a slave clock to a clock signal of the RF signal when the load impedance is resistive only or when the clock signal of the RF signal has a given phase condition.